US5103167A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit device provided with test mode function
Assignee: Sharp Corp
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Filing: 1990-08-24
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Granted: 1992-04-07
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Expires: 2010-08-24
Abstract
Abstract An integrated circuit device provided with test mode function has a plurality of terminals used for receiving and/or feeding out signals during a normal operation of the device. At least one terminal of the plurality of terminals are connected to a register for storing test mode setting data applied through the at least one terminal during a reset cycle period of the device. In accordance with the test mode setting data stored in the register, a setting of a predetermined test mode of the device is executed.
Inventors
- 👤 Nobuhiro Okano
- 👤 Hiroshi Uemura
- 👤 Eiji Ogino
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 06:29
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31701
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
117 words
An integrated circuit device provided with test mode function comprising: a plurality of terminals used for receiving and/or feeding out signals during a normal operation of said device; a reset terminal for receiving a reset signal applied thereto during a reset cycle period of said device; and a register means disposed in said device and connected to at least one predetermined terminal of said plurality of terminals and to said reset terminal, for storing test mode setting data applied through said at least one predetermined terminal, said register means having means for allowing said register to store said test mode setting data into said register means only when the reset signal is applied through said reset terminal.
Claim 2
Dependent Claim
117 words
An integrated circuit device provided with test mode function comprising: a plurality of terminals used for receiving and/or feeding out signals during a normal operation of said device; a reset terminal for receiving a reset signal applied thereto during a reset cycle period of said device; and a register means disposed in said device and connected to at least one predetermined terminal of said plurality of terminals and to said reset terminal, for storing test mode setting data applied through said at least one predetermined terminal, said register means having means for allowing said register to store said test mode setting data into said register means only when the reset signal is applied through said reset terminal.
Claim 3
Dependent Claim
27 words
An integrated circuit device as claimed in claim 1, wherein said plurality of terminals are kept in high impedance during the reset cycle period of said device.
Claim 4
Dependent Claim
30 words
An integrated circuit device as claimed in claim 1, wherein said device includes a central processing unit and said plurality of terminals are directly connected to said central processing unit.
Claim 5
Dependent Claim
25 words
An integrated circuit device as claimed in claim 3, wherein said plurality of terminals are a plurality of input terminals used for receiving input signals.
Claim 6
Dependent Claim
26 words
An integrated circuit device as claimed in claim 3, wherein said plurality of terminals are a plurality of output terminals used for feeding out output signals.
Claim 7
Dependent Claim
28 words
An integrated circuit device as claimed in claim 1, wherein said register has a capacity for spring the test mode setting data having a predetermined number of bits.
Claim 8
Dependent Claim
39 words
An integrated circuit device as claimed in claim 6, wherein said register includes a plurality of serially connected flip-flops and an AND gate, the number of said flip-flops being equal to said predetermined number of bits of said register.
Claim 9
Dependent Claim
56 words
An integrated circuit device as claimed in claim 1, wherein said means for allowing of said register includes an AND gate having at least two inputs, one of which is connected to said reset terminal so as to allow storing of said test mode setting data into said register means in response to the reset signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-04-07 | 1995-10-07 | 1996-04-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-04-07 | 1999-10-07 | 2000-04-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-04-07 | 2003-10-07 | 2004-04-07 | $7700.00 | Window Closed / Lapsed |