Apparatus for processing signalling messages in an asynchronous time division telecommunications network

Claim 2

Apparatus for processing signalling messages in an asynchronous time division telecommunications network in which information of all kinds is interchanged by means of cells using a communications protocol adapted to asynchronous time division, each cell being preceded by a header which includes a virtual circuit number, said signalling messages being interchanged between control stations connected to the telecommunications network and being exploited within control stations, wherein the apparatus is implanted in each control station for connecting the station to the telecommunications network, wherein it includes a first processor connected to the telecommunications network, a memory, a transmit control memory, a receive control memory, a data bus connected to the first processor, to the memory, and to the control memories, an address bus connected to the first processor and to the memory, and a third bus connected to the memory, to the control memories, and to a second processor situated within said station and exploiting said messages, and wherein the first processor performs the following: detecting transmission errors cell-by-cell, detecting lost or added cells, splitting up a signalling message from the higher level processor into cells, and de-interlacing cells on reception belonging to a plurality of different signalling messages.

Claim 3

Apparatus according to claim 1, wherein the memory comprises a transmit memory and a receive memory, wherein the transmit memory comprises a first transmit zone and a second transmit zone for storing the messages to be transmitted as delivered by the second processor, first and second memory words associated with the first and second transmit zones, each including an end-of-message flag sent by the first processor at the ends of messages transmitted or read by the latter, and a transmit context portion having one transmit context per virtual circuit processed by the first processor, each transmit context specifying a number of a cell to be transmitted and acting as a transmitted cell counter, and wherein the receive memory comprises a data portion constituted by information zones each corresponding to an information field of a cell, by a descriptor portion having as many descriptors as there are information zones, each descriptor having a first flag specifying the state of the corresponding information zone, a second flag for indicating whether the zone contains the beginning of a message, a third flag for indicating whether the zone contains the end of the message, and also giving the number of information bytes stored in the said zone and the number of the virtual circuit over which the contents of the zone was received, a clock counter register, a third memory word having an overflow flag, and a receive context portion having one receive context per virtual circuit processed by the processor circuit, each receive context giving the address of a descriptor corresponding to a zone containing the beginning of a message, and giving a next expected cell number, and having a fourth flag for specifying that a message comprising a plurality of cells is in the process of being received over the virtual circuit corresponding to said receive context.

Claim 4

Apparatus according to claim 2, wherein the transmit control memory is of the FIFO type, written to by the second processor and read from by the first processor, the higher level processor delivering a transmit command for each message to be transmitted, the transmit command indicating the transmit zone in which the message is stored, the number of bytes in said message, and the number of the virtual circuit over which said message is to be transmitted.

Claim 5

Apparatus according to claim 3, wherein the receive control memory is of the FIFO type, written to by the first processor and read from by the second processor, the first processor delivering, for each receive message, a receive command indicating an information zone number in the receive memory containing the beginning of a message, and the time at which said command was delivered.

Claim 6

Apparatus according to claim 1, wherein in order to detect transmission errors cell-by-cell, each cell includes a cyclic redundancy check indication performed over the entire cell.

Claim 7

Apparatus according to claim 1, wherein the memory is a two-port memory.