US5101201A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for converting scan data of a keyboard
Assignee: Samsung Electronics Co Ltd
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Filing: 1990-05-16
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Granted: 1992-03-31
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Expires: 2010-05-16
Abstract
Abstract There is disclosed a circuit for converting scan data comprising a key matrix switch having multiple keys and multiple mode selecting switches for producing scan data when one of said keys is activated, a scan decoder for decoding said scan data to produce a mode selecting signal, first scan data, second scan data, and first and second clock signals respectively synchronized with said first and second scan data, first and second latch circuits for latching said first and second scan data according to said first and second clock signals, and a mode selecting adder for converting the first and second latched output data of said first and second latch circuits into the first and second converted scan data according to the mode selecting signal of said scan decoder, whereby scan data of a different modes may be produced according to the operation of said mode selecting switches.
Inventors
- 👤 Woo-Sung Choi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:30
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03M; H03M11/00; H03M11/02; H03M11/04; H03M11/14
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
154 words
A circuit for converting scan data, comprising: a key matrix having a plurality of keys and a plurality of mode selecting switches for producing the scan data when one of the keys is activated, said plurality of keys being arranged in a matrix structure; a scan decoder for decoding said scan data to produce a mode selecting signal, first scan data, second scan data, and first and second clock signals respectively synchronized with said first and second scan data; first and second latch circuits for latching said first and second scan data according to said first and second clock signals; and a mode selecting adder for converting first and second latched output data of said first and second latch circuits into first and second connected data according to the mode selecting signal of said scan decoder, whereby scan data of different modes may be produced according to the operation of said mode selecting switches.
Claim 2
Dependent Claim
154 words
A circuit for converting scan data, comprising: a key matrix having a plurality of keys and a plurality of mode selecting switches for producing the scan data when one of the keys is activated, said plurality of keys being arranged in a matrix structure; a scan decoder for decoding said scan data to produce a mode selecting signal, first scan data, second scan data, and first and second clock signals respectively synchronized with said first and second scan data; first and second latch circuits for latching said first and second scan data according to said first and second clock signals; and a mode selecting adder for converting first and second latched output data of said first and second latch circuits into first and second connected data according to the mode selecting signal of said scan decoder, whereby scan data of different modes may be produced according to the operation of said mode selecting switches.
Claim 3
Dependent Claim
40 words
A can data conversion circuit as claimed in claim 1, characterized by said key matrix having a plurality of crossing rows and columns and one key at each of the cross points where said multiple rows cross said multiple columns.
Claim 4
Dependent Claim
91 words
A scan data conversion circuit as claimed in claim 1, wherein said mode selecting adder comprises: means for receiving said first and second latched output data of said first and second latch circuits; means for receiving said mode selecting signal of said scan decoder to determine an operational mode; means for converting said first and second latched output data into said first converted data according to said operational mode; and means for converting said first and second latched output data into said second converted scan data according to said operational mode.
Claim 5
Dependent Claim
100 words
The scan data conversion circuit of claim 1, wherein said mode selecting adder comprises: option data input lines for receiving said mode selecting signal; first input data lines for receiving said first latched output data; second input data lines for receiving said second latched output data; first and second converted scan data output means; first logical operation means for connecting said option data lines, said first input data lines and said first converted scan data output means; second logical operation means for connecting said option data lines, said second input data lines and said second converted scan data output means.
Claim 6
Dependent Claim
48 words
The scan data conversion circuit of claim 4, said option data input lines including: first and second key state input lines; said first key state input line connected to said first logical operation means; and said second key state input line connected to said second logical operation means.
Claim 7
Dependent Claim
39 words
The scan data conversion circuit of claim 4, said first and second logical operation means comprises: logic means for combining said first and second latched data with said mode selecting signal to produce said first and second converted data.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-31 | 1995-09-30 | 1996-03-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-31 | 1999-09-30 | 2000-03-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-31 | 2003-09-30 | 2004-03-31 | $7700.00 | Window Closed / Lapsed |