Digital computer code word identification system

Claim 3

The method of claim 1 wherein the step of programming comprises opening desired fuses in the PAL.

Claim 4

The method of claim 2, further comprising the step of counting the portion and the remaining portion of the array code word, a count thereby identifying the portion and the remaining portion of the CPU.

Claim 5

The method of claim 3 wherein the program code word and the array code word each comprise twenty-four bits.

Claim 6

The method of claim 4 wherein the portion of the array code word comprises four bits, in the step of subsequently reading the remaining portion comprises reading five subsequent times at the same address of the logic array, providing four-bit segments each time.

Claim 7

A digital computer system, including a central processor unit (CPU) and a memory, comprising: (a) a computer program stored in the memory of the digital computer system for execution thereof, the program having a program code word embedded at an arbitrary location therein; (b) an addressable identification logic array, operatively connected to the CPU for receiving a read signal originated by the CPU at an address of the logic array, the logic array being programmed to output a portion of a preset array code word in response to the read signal at the address of the logic array and the remaining portion of the array code word in response to at least one subsequent read signal at the same address of the logic array, the logic array comprising a counter for counting the read signal and the at least one subsequent read signal to identify the portion and the remaining portion of the array code word to enable the logic array to output the portion and the remaining portion in the proper sequence; and (c) a data bus, connected to the logic array and the CPU for transmitting the portion and the remaining portion of the array code word to the CPU for comparison with the programmed code word by the CPU to permit execution of the program by the CPU when the program code word and the array code word are identical, and to not permit execution of the program when the program code word and the array code word are not identical.

Claim 8

A digital computer system, including a central processor unit (CPU) and a memory, comprising: (a) a computer program stored in the memory of the digital computer system for execution thereof, the program having a program code word embedded at an arbitrary location therein; (b) an addressable identification logic array, operatively connected to the CPU for receiving a read signal originated by the CPU at an address of the logic array, the logic array being programmed to output a portion of a preset array code word in response to the read signal at the address of the logic array and the remaining portion of the array code word in response to at least one subsequent read signal at the same address of the logic array, the logic array comprising a counter for counting the read signal and the at least one subsequent read signal to identify the portion and the remaining portion of the array code word to enable the logic array to output the portion and the remaining portion in the proper sequence; and (c) a data bus, connected to the logic array and the CPU for transmitting the portion and the remaining portion of the array code word to the CPU for comparison with the programmed code word by the CPU to permit execution of the program by the CPU when the program code word and the array code word are identical, and to not permit execution of the program when the program code word and the array code word are not identical.

Claim 9

The system of claim 6 wherein the logic array further comprises a programmable array of logic (PAL), programmed externally of the system by opening selected fuses to form the logic array.

Claim 10

The system of claim 7 wherein the PAL comprises a security fuse, opened and positioned in the logic array to prevent identifying the opened fuses.

Claim 11

The system of claim 8 wherein the program code word and the array code word each comprise twenty-four bits.

Claim 12

The system of claim 9 wherein the portion of the array code word comprises four bits, and the at least one subsequent read signal includes five subsequent read signals, causing the PAL to output four-bit segments for each subsequent read signal.

Claim 13

The system of claim 10 wherein the PAL further comprises a first plurality of input pins, selectively tied to high and low voltages to encode a system model type, and to transfer the encoded system model type to the data bus at a first predetermined count of the counter.

Claim 14

The system of claim 11 wherein the PAL further comprises a second plurality of input pins, selectively tied to high and low voltages to encode a number of a present system revision, and to transfer the number to the data bus at a second predetermined count of the counter.