US5099452A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory including reduced capacitive coupling between adjacent bit lines
Assignee: NEC Electronics Corp
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Filing: 1989-06-27
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Granted: 1992-03-24
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Expires: 2009-06-27
Abstract
Abstract A semiconductor memory apparatus comprises a plurality of complementary bit line pairs for accessing memory cells. Each of the memory cells is accessed by two complementary bit line pairs. Each of the complementary bit line pairs is connected to a corresponding sense amp circuit for amplifying a signal level difference between bit lines of a corresponding bit line pair. A plurality of sealed lines, each being connected to ground and being positioned between two adjacent bit lines of different complementary bit line pairs, are provided to avoid the formation of a line-to-line capacitance between the two adjacent bit lines.
Inventors
- 👤 Hiroyuki Yamakoshi
- 👤 Hidehiro Asai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 21:18
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/18; G11C5/00; G11C5/06; G11C5/063; G11C8/00; G11C8/16
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
152 words
A semiconductor apparatus, comprising: a predetermined number of memory cells, each storing a binary information; a plurality of complementary bit line paris, wherein two of said complementary bit line pairs are coupled to a corresponding memory cell of said memory cells, and wherein two of said complementary bit line pairs are accessible to each of said corresponding memory cell; a plurality of sense amplifier circuits, each of said sense amplifier circuits being connected to a corresponding one of said complementary bit line pairs for amplifying a signal level difference between bit lines of said corresponding complementary bit line pair; and a plurality of grounded lines, each of said grounded lines having a fixed potential and being provided between adjacent ones of said complementary bit line pairs so as to avoid the formation of a line-to-line capacitance which is normally produced between two adjacent bit lines of different adjacent complementary bit line pairs.
Claim 2
Dependent Claim
152 words
A semiconductor apparatus, comprising: a predetermined number of memory cells, each storing a binary information; a plurality of complementary bit line paris, wherein two of said complementary bit line pairs are coupled to a corresponding memory cell of said memory cells, and wherein two of said complementary bit line pairs are accessible to each of said corresponding memory cell; a plurality of sense amplifier circuits, each of said sense amplifier circuits being connected to a corresponding one of said complementary bit line pairs for amplifying a signal level difference between bit lines of said corresponding complementary bit line pair; and a plurality of grounded lines, each of said grounded lines having a fixed potential and being provided between adjacent ones of said complementary bit line pairs so as to avoid the formation of a line-to-line capacitance which is normally produced between two adjacent bit lines of different adjacent complementary bit line pairs.
Claim 3
Dependent Claim
47 words
A semiconductor memory apparatus according to claim 1, wherein at least one of said grounded lines is disposed so as to respectively provide an equal capacitance value between two adjacent bit lines of different complementary bit line pairs and said at least one of said grounded lines.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-24 | 1995-09-23 | 1996-03-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-24 | 1999-09-23 | 2000-03-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-24 | 2003-09-23 | 2004-03-24 | $7700.00 | Window Closed / Lapsed |