US5099331A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for overlaying a displayed image with a second image
Assignee: Texas Instruments Inc
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Filing: 1990-02-28
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Granted: 1992-03-24
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Expires: 2010-02-28
Abstract
Abstract A video system is disclosed which is capable of receiving digital data from a source such as a video camera, and subsequently transferring the received data into a main frame buffer for display on a video display, where the data from the source can overlay a primary image stored in the main frame buffer. An auxiliary frame buffer, consisting of a bank of dual-port RAMs, receives the data of the overlay image via its serial port and transfers this data into the randomly accessible array therein. A direct-memory-access (DMA) operation performs the transfer from the auxiliary frame buffer into the main frame buffer, with the source and destination positions in the auxiliary and main frame buffers, respectively, independently selectable. The performance of the DMA operation can be enhanced by simultaneously performing a page mode read of the auxiliary frame buffer with a page mode write to the main frame buffer.
Inventors
- 👤 Loc Truong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 09:29
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/222; H04N5/262; H04N5/272; G; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G09G5/395; G09G5/397; G09G2340/00; G09G2340/12; G09G2340/125
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
195 words
A display system, comprising: display means for providing a visual display; a first frame buffer, connected to the said display means, for storing data representative of a primary image to be displayed by said display means; a data source, for providing data corresponding to an overlay image; a second frame buffer, connected to said date source, for storing data presented by said data source; a first addressing means, connected to said first frame buffer, for presenting address and control signals thereto; a second addressing means, connected to said second frame buffer, for presenting address and control signals thereto; a data bus, connected between said first and second frame buffers, for communication data therebetween, so that the contents of said second frame buffer containing said overlay image may be communicated to said first frame buffer for writing thereinto; wherein said second frame buffer comprises a bank of dual-port random access memories, said dual-port random memories each including: a serial input, connected to said data source, for receiving serial input data therefrom; an array of randomly addressable memory cells; a random access port for presenting the contents of the memory cell selected by said second addressing means.
Claim 2
Dependent Claim
195 words
A display system, comprising: display means for providing a visual display; a first frame buffer, connected to the said display means, for storing data representative of a primary image to be displayed by said display means; a data source, for providing data corresponding to an overlay image; a second frame buffer, connected to said date source, for storing data presented by said data source; a first addressing means, connected to said first frame buffer, for presenting address and control signals thereto; a second addressing means, connected to said second frame buffer, for presenting address and control signals thereto; a data bus, connected between said first and second frame buffers, for communication data therebetween, so that the contents of said second frame buffer containing said overlay image may be communicated to said first frame buffer for writing thereinto; wherein said second frame buffer comprises a bank of dual-port random access memories, said dual-port random memories each including: a serial input, connected to said data source, for receiving serial input data therefrom; an array of randomly addressable memory cells; a random access port for presenting the contents of the memory cell selected by said second addressing means.
Claim 3
Dependent Claim
66 words
The system of claim 1, wherein said first frame buffer comprises a bank of dual-port random access memories, said dual-port random access memories each including; a serial output, connected to said display means, for presenting serial output data thereto; an array of randomly addressable memory cells; a random access port for receiving data to be stored in the memory cell selected by said first addressing means.
Claim 4
Dependent Claim
197 words
A display system, comprising: display means for providing a visual display; a first frame buffer, connected to the said display means, for storing data representative of a primary image to be displayed by said display means; a data source, for providing data corresponding to an overlay image; a second frame buffer, connected to said data source, for storing data presented by said data source; a first addressing means, connected to said first frame buffer, for presenting address and control signals thereto; a second addressing means, connected to said second frame buffer, for presenting address and control signals thereto; a data bus, connected between said first and second frame buffers, for communicating data therebetween, so that the contents of said second frame buffer containing said overlay image may be communicated to said first frame buffer for writing thereinto; wherein said first frame buffer comprises a bank of dual-port random access memories, said dual-port random memories each including: a serial output, connected to said display means, for presenting serial output data thereto; an array of randomly addressable memory cells; a random access port for receiving data to be stored in the memory cell selected by said first addressing means.
Claim 5
Dependent Claim
197 words
A display system, comprising: display means for providing a visual display; a first frame buffer, connected to the said display means, for storing data representative of a primary image to be displayed by said display means; a data source, for providing data corresponding to an overlay image; a second frame buffer, connected to said data source, for storing data presented by said data source; a first addressing means, connected to said first frame buffer, for presenting address and control signals thereto; a second addressing means, connected to said second frame buffer, for presenting address and control signals thereto; a data bus, connected between said first and second frame buffers, for communicating data therebetween, so that the contents of said second frame buffer containing said overlay image may be communicated to said first frame buffer for writing thereinto; wherein said first frame buffer comprises a bank of dual-port random access memories, said dual-port random memories each including: a serial output, connected to said display means, for presenting serial output data thereto; an array of randomly addressable memory cells; a random access port for receiving data to be stored in the memory cell selected by said first addressing means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-24 | 1995-09-23 | 1996-03-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-24 | 1999-09-23 | 2000-03-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-24 | 2003-09-23 | 2004-03-24 | $7700.00 | Window Closed / Lapsed |