US5094983A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for manufacture of an integrated mos semiconductor array
Assignee: Telefunken Electronic GmbH
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Filing: 1990-10-09
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Granted: 1992-03-10
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Expires: 2010-10-09
Abstract
Abstract A method of manufacture of an integrated MOS semiconductor array for the low-frequency range having MOS components and circuit paths arranged on a semiconductor substrate. Exposed surfaces between the circuit paths are made hydrophobic by germinating with hexamethyl disilazane ((CH 3 ) 3 SiNHSi(CH 3 ) 3 ), so that the occurrence of leakage currents is avoided. In addition, in an integrated MOS semiconductor array in which the MOS components and the circuit path are covered with a protective layer, the surface of this protective layer is made hydrophobic. As a result, both leakage currents and parasitic capacitances are prevented.
Inventors
- 👤 Josef Furthaler
- 👤 Friedemann Gschwend
- 👤 Manfred Ohagen
- 👤 Peter Tomaszewski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 22:55
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/01; H10W20/00; H10W20/40; H10W20/495
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
60 words
In a method of manufacture of an integrated MOS semiconductor array for the low-frequency range which includes forming MOS components and circuit paths on a semiconductor substrate, the method further comprising: making exposed surfaces between the circuit paths hydrophobic by germinating with hexamethyl disilazane ((CH 3 ) 3 SiNHSi(CH 3 ) 3 ) to form a reaction product with water.
Claim 2
Dependent Claim
60 words
In a method of manufacture of an integrated MOS semiconductor array for the low-frequency range which includes forming MOS components and circuit paths on a semiconductor substrate, the method further comprising: making exposed surfaces between the circuit paths hydrophobic by germinating with hexamethyl disilazane ((CH 3 ) 3 SiNHSi(CH 3 ) 3 ) to form a reaction product with water.
Claim 3
Dependent Claim
30 words
The method of claim 1, wherein germinating comprises: flowing an inert carrier gas with finely dispersed hexamethyl disilazane ((CH 3 ) 3 SiNHSi(CH 3 ) 3 ) over the surfaces.
Claim 4
Independent Claim
72 words
A method of manufacture of an integrated MOS semiconductor array for the low-frequency range which includes forming MOS components and circuit paths on a semiconductor substrate and covering said MOS components and said circuit paths with a protective layer, the method further comprising: making exposed surfaces of the protective layer hydrophobic by germinating with hexamethyl disilazane ((CH 3 ) 3 SiNHSi(CH 3 ) 3 ) to form a reaction product with water.
Claim 5
Independent Claim
72 words
A method of manufacture of an integrated MOS semiconductor array for the low-frequency range which includes forming MOS components and circuit paths on a semiconductor substrate and covering said MOS components and said circuit paths with a protective layer, the method further comprising: making exposed surfaces of the protective layer hydrophobic by germinating with hexamethyl disilazane ((CH 3 ) 3 SiNHSi(CH 3 ) 3 ) to form a reaction product with water.
Claim 6
Dependent Claim
22 words
A method according to claim 3, wherein the protective layer comprises silicon dioxide (SiO 2 ) formed by CVD (chemical vapour deposition).
Claim 7
Dependent Claim
24 words
A method according to claim 3, wherein the protective layer comprises silicon dioxide (SiO 2 ) formed by PECVD (plasma enhanced chemical vapour deposition).
Claim 8
Dependent Claim
18 words
A method according to claim 3, wherein the protective layer comprises silicon nitride (Si 3 N 4 ).
Claim 9
Dependent Claim
30 words
The method of claim 3, wherein germinating comprises: flowing an inert carrier gas with finely dispersed hexamethyl disilazane ((CH 3 ) 3 SiNHSi(CH 3 ) 3 ) over the surfaces.
Claim 10
Independent Claim
70 words
A method of manufacturing an integrated MOS device, comprising the steps of: forming MOS components and circuit paths on a substrate; making exposed surfaces of the MOS components and circuit paths hydrophobic by treating the surfaces with hexamethyl disilazane ((CH 3 ) 3 SiNHSi(CH 3 ) 3 ) to react with water and produce a hydrophobic reaction product on the surfaces; and probing the device to test the MOS components.
Claim 11
Independent Claim
70 words
A method of manufacturing an integrated MOS device, comprising the steps of: forming MOS components and circuit paths on a substrate; making exposed surfaces of the MOS components and circuit paths hydrophobic by treating the surfaces with hexamethyl disilazane ((CH 3 ) 3 SiNHSi(CH 3 ) 3 ) to react with water and produce a hydrophobic reaction product on the surfaces; and probing the device to test the MOS components.
Claim 12
Dependent Claim
15 words
The method of claim 8, wherein the reaction product is created with separation of ammonia.
Claim 13
Dependent Claim
18 words
The method of claim 8, wherein the exposed surfaces are an insulating layer having the circuit paths thereon.
Claim 14
Dependent Claim
23 words
The method of claim 8, wherein the exposed surfaces are on a protective layer over an insulating layer having the circuit paths thereon.
Claim 15
Dependent Claim
21 words
The method of claim 11, wherein the protective layer comprises silicon dioxide (SiO 2 ) formed by CVD (chemical vapour deposition).
Claim 16
Dependent Claim
23 words
The method of claim 11, wherein the protective layer comprises silicon dioxide (SiO 2 ) formed by PECVD (plasma enhanced chemical vapour deposition).
Claim 17
Dependent Claim
17 words
The method of claim 11, wherein the protective layer comprises silicon nitride (Si 3 N 4 ).
Claim 18
Dependent Claim
27 words
The method of claim 8, wherein the step of making exposed surfaces hydrophobic comprises flowing an inert carrier gas finely distributed in hexamethyl disilazane over the surfaces.
Claim 19
Dependent Claim
27 words
The method of claim 15, wherein the exposed surfaces are oriented in one of a horizontal and a vertical direction with respect to the carrier gas flow.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-10 | 1995-09-09 | 1996-03-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-10 | 1999-09-09 | 2000-03-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-10 | 2003-09-09 | 2004-03-10 | $7700.00 | Window Closed / Lapsed |