Fast calculation circuit for cyclic redundancy check code

Claim 1

A fast calculation circuit to calculate a cyclic redundancy check code for compressed raw data having a compressed area and an uncompressed area, said compressed area containing a content byte, a compression mark and a number byte, said content byte being representative of a plurality of consecutive identical raw data bytes before compression, said number bytes being representative of a total number of the plurality of consecutive identical raw data bytes before compression, and said compression mark designating the compressed area, comprising: first calculation means for calculating a cyclic redundancy check code of data in said uncompressed area on the basis of a generating polynomial; second calculation means for calculating a cyclic redundancy check code of data in said compressed area on the basis of the content byte and number byte contained in said compressed data; detection means for detecting said compressed area by detecting the compression mark and said uncompressed area prior to cyclic redundancy check code calculation; and means, connected to the detection means and to said first and said second calculation means, for selecting either a first output of said first calculation means when the detection means detects the compressed area or a second output of said second calculation means when the detection means detects the uncompressed area; wherein when said detection means detects said compressed area, a cyclic redundancy check code of data in said compressed area is calculated by said second calculation means, and when said detection means detects said uncompressed area, a cyclic redundancy check code of data in said uncompressed area is calculated by said first calculation means.