US5093808A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Folded bitline dynamic ram with reduced shared supply voltages
Assignee: Mosaid Technologies Inc
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Filing: 1990-09-19
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Granted: 1992-03-03
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Expires: 2010-09-19
Abstract
Abstract A folded bitline dynamic RAM circuit with reduced shared supply voltages comprised of circuitry for applying full logic high and low supply voltages to respective bitlines during successive active cycles of the RAM circuit, and circuitry for applying reduced supply voltages to the bitlines during successive precharge cycles. By applying reduced supply voltages to the bitlines during the precharge cycles voltage stress on cell access transistors and sense amplifiers of the RAM circuit are reduced. The time required to share the charge residing on the bitline halves at the start of the active cycle is also reduced.
Inventors
- 👤 Richard C. Foss
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 10:15
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4074; G11C11/409; G11C11/4094
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
185 words
A method of accessing and refreshing data stored on one or more storage capacitors connected via corresponding cell access transistors to respective bitlines in a dynamic RAM circuit, during successive active and precharge operating cycles of said circuit, comprising the steps of: a) applying reduced high and low supply voltages to respective ones of said bitlines during said precharge cycle, said reduced high and low supply voltages being less than and greater than said full high and low supply voltages, respectively, b) ceasing application of said reduced supply voltages to said bitlines and interconnecting said bitlines at the start of said active cycle, for equalizing charge on said bitlines, c) connecting said cell access transistors to said bitlines for transferring said data from said storage capacitors to said bitlines and thereafter sensing said data transferred to said bitlines, whereby said data is accessed, d) applying full high and low supply voltages to said respective bitlines for restoring said data on said storage capacitors, whereby said data is refreshed, and e) disconnecting said cell access transistors from said bitlines at the end of said active cycle.
Claim 2
Independent Claim
185 words
A method of accessing and refreshing data stored on one or more storage capacitors connected via corresponding cell access transistors to respective bitlines in a dynamic RAM circuit, during successive active and precharge operating cycles of said circuit, comprising the steps of: a) applying reduced high and low supply voltages to respective ones of said bitlines during said precharge cycle, said reduced high and low supply voltages being less than and greater than said full high and low supply voltages, respectively, b) ceasing application of said reduced supply voltages to said bitlines and interconnecting said bitlines at the start of said active cycle, for equalizing charge on said bitlines, c) connecting said cell access transistors to said bitlines for transferring said data from said storage capacitors to said bitlines and thereafter sensing said data transferred to said bitlines, whereby said data is accessed, d) applying full high and low supply voltages to said respective bitlines for restoring said data on said storage capacitors, whereby said data is refreshed, and e) disconnecting said cell access transistors from said bitlines at the end of said active cycle.
Claim 3
Dependent Claim
159 words
A modified dynamic RAM circuit, comprised of: a) a plurality of memory cells for storing data therein, b) a plurality of pairs of bitlines, c) means for applying high and low voltages which are less than and greater than the full high and low supply voltages respectively to respective bitlines of said bitlines pairs for precharging said bitlines, and thereafter ceasing application of said voltages, d) means for subsequently interconnecting respective bitlines of each of said bitline pairs for equalizing charge thereon, and thereafter disconnecting said respective bitlines, e) means for connecting said plurality of memory cells to said respective bitlines for transferring said data onto said bitlines, and f) means for applying full high and low supply voltages to said respective ones of said bitlines for sensing said data transferred thereto and for restoring said data in said memory cells, whereby applying said reduced supply voltages to said bitlines results in reduced voltage stress and quick data access.
Claim 4
Dependent Claim
159 words
A modified dynamic RAM circuit, comprised of: a) a plurality of memory cells for storing data therein, b) a plurality of pairs of bitlines, c) means for applying high and low voltages which are less than and greater than the full high and low supply voltages respectively to respective bitlines of said bitlines pairs for precharging said bitlines, and thereafter ceasing application of said voltages, d) means for subsequently interconnecting respective bitlines of each of said bitline pairs for equalizing charge thereon, and thereafter disconnecting said respective bitlines, e) means for connecting said plurality of memory cells to said respective bitlines for transferring said data onto said bitlines, and f) means for applying full high and low supply voltages to said respective ones of said bitlines for sensing said data transferred thereto and for restoring said data in said memory cells, whereby applying said reduced supply voltages to said bitlines results in reduced voltage stress and quick data access.
Claim 5
Dependent Claim
73 words
A modified dynamic RAM circuit as defined in claim 2, wherein said means for applying reduced supply voltages to said bitlines is comprised of a pair of saturation mode field effect transistors connected to sources of said full high and low supply voltages, and via respective additional gate transistors to said respective bitlines, whereby said full supply voltages are reduced as a result of voltage drop across said saturation mode field effect transistors.
Claim 6
Dependent Claim
182 words
A modified dynamic RAM circuit as defined in claim 3, wherein said means for applying full high and low supply voltages is comprised of: a) pair of P-channel cross-coupled field effect transistors connected to said respective bitlines, b) a further P-channel transistor for receiving an enable signal on a gate terminal thereof and in response interconnecting said full high supply voltage to said pair of cross-coupled transistors via a source-drain circuit path of said further transistor, for charging a predetermined bitline of each of said pairs of bitlines to said full logic high supply voltage, c) a pair of N-channel cross-coupled field effect transistors connected to said respective bitlines, and d) a further N-channel transistor for receiving an enable signal on a gate terminal thereof and in response interconnecting said full low supply voltage to said pair of N-channel cross-coupled transistors via a source, drain circuit path of said further N-channel transistor, for charging the other bitline of each of said pairs of bitlines to said full logic low supply voltage, thereby creating an enhanced voltage differential across said respective bitline pairs.
Claim 7
Dependent Claim
183 words
A modified dynamic RAM circuit as defined in claim 2, wherein said means for applying full high and low supply voltages is comprised of: a) a pair of P-channel cross-coupled field effect transistors connected to said respective bitlines, b) a further P-channel transistor for receiving an enable signal on a gate terminal thereof and in response interconnecting said full high supply voltage to said pair of cross-coupled transistors via a source-drain circuit path of said further transistor, for charging a predetermined bitline of each of said pairs of bitlines to said full logic high supply voltage, c) a pair of N-channel cross-coupled field effect transistors connected to said respective bitlines, and d) a further N-channel transistor for receiving an enable signal on a gate terminal thereof and in response interconnecting said full low supply voltage to said pair of N-channel cross-coupled transistors via a source drain circuit path of said further N-channel transistor, for charging the other bitline of each of said pairs of bitlines to said full logic low supply voltage, thereby creating an enhanced voltage differential across said respective bitline pairs.
References Cited (Backward Citations)
US4780850A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-03 | 1995-09-02 | 1996-03-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-03 | 1999-09-02 | 2000-03-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-03 | 2003-09-02 | 2004-03-03 | $7700.00 | Window Closed / Lapsed |