Overvoltage protection in series thyristor string for static var compensator

Claim 2

A gate pulse generator for a static var compensator, comprising: a thyristor switch being formed of a first block of series-connected thyristors and a second block of series-connected thyristors, said second block being anti-parallel connected to said first block; first detector means for detecting a first voltage applied across said thyristor switch to generate a first voltage signal when the first block thyristors is forwardly biased; first firing means for firing said first block thyristors in accordance with a first conduction period signal and said first voltage signal; first expanding means for expanding by a first predetermined period an active period of said first conduction period signal from time when said first voltage is substantially zero; second detector means for detecting a second voltage applied across said thyristor switch to generate a second voltage signal when the second block thyristors is forwardly biased; second firing means for firing said second block thyristors in accordance with a second conduction period signal and said second voltage signal; and second expanding means for expanding by a second predetermined period an active period of said second conduction period signal from time when said second voltage is substantially zero.

Claim 3

A gate pulse generator according to claim 1, wherein said thyristor switch is provided with a capacitor connected in series thereto, said thyristor switch and said capacitor constituting a thyristor switched capacitor.

Claim 4

A gate pulse generator according to claim 1, wherein said thyristor switch is provided with a reactor connected in series thereto, said thyristor switch and said reactor constituting a thyristor switched reactor.

Claim 5

A gate pulse generator according to claim 1, wherein said second firing means includes second generator means for generating s aid second conduction period signal when both said second phase signal and said ON signal are generated.

Claim 6

A gate pulse generator according to claim 4, wherein said second generator means includes means for terminating the active period of said second conduction period signal, after elapsing said second predetermined period running from a time when both said first and second voltages are substantially zero.

Claim 7

A gate pulse generator according to claim 1, wherein said first generator means includes means for terminating the active period of said first conduction period signal, after elapsing said first predetermined period running from a time when both said first and second voltages are substantially zero.

Claim 8

A gate pulse generator according to claim 1, further comprising: means for generating a first phase signal when said first block thyristors is to be turned on, a second phase signal when said second block thyristors is to be turned on, and an ON signal when said thyristor switched capacitor is to be activated, wherein said first expanding means includes: first delay means for delaying a logical AND of said second phase signal and said ON signal by a first delay time to provide a first delayed signal; first AND means for detecting a first logical AND of said first delayed signal, an inverted logic level of said first voltage signal, and an inverted logic level of said second voltage signal; second delay means for delaying said first logical AND by said first predetermined period to provide a second delayed signal; and a first flip-flop which is set by a logical AND of said first phase signal and said ON signal to activate said first conduction period signal, and which is reset by said second delayed signal to inactivate said first conduction period signal.

Claim 9

A gate pulse generator according to claim 7, wherein said second expanding means includes: third delay means for delaying a logical AND of said first phase signal and said ON signal by a second delay time to provide a third delayed signal; second AND means for detecting a second logical AND of said second delayed signal, an inverted logic level of said first voltage signal, and an inverted logic level of said second voltage signal; fourth delay means for delaying said second logical AND by said second predetermined period to provide a fourth delayed signal; and a second flip-flop which is set by a logical AND of said second phase signal and said ON signal to activate said second conduction period signal, and which is reset by said fourth delayed signal to inactivate said second conduction period signal.

Claim 10

A gate pulse generator, comprising: a thyristor switch being formed of a first block of series-connected thyristors and a second block of series-connected thyristors, said second block being anti-parallel connected to said first block; first detector means for detecting a first voltage applied across said thyristor switch to generate a first voltage signal when the first block thyristors is forwardly biased; first firing means for firing said first block thyristors in accordance with a first conduction period signal and said first voltage signal; first expanding means for expanding by a first predetermined period an active period of said first conduction period signal from time when said first voltage is substantially zero; second detector means for detecting a second voltage applied across said thyristor switch to generate a second voltage signal when the second block thyristors is forwardly biased; second firing means for firing said second block thyristors in accordance with a second conduction period signal and said second voltage signal; and second expanding means for expanding by a second predetermined period an active period of said second conduction period signal from time when said second voltage is substantially zero; means for generating a first phase signal when said first block thyristors are too be turned on, a second phase signal when said second block thyristors are to be turned on, and an ON signal when said thyristor switched capacitor is to be activated, wherein said first firing means includes first generator means for generating said first conduction period signal when both said first phase signal and said ON signal are generated.

Claim 11

A gate pulse generator, comprising: a thyristor switch being formed of a first block of series-connected thyristors and a second block of series-connected thyristors, said second block being anti-parallel connected to said first block; first detector means for detecting a first voltage applied across said thyristor switch to generate a first voltage signal when the first block thyristors is forwardly biased; first firing means for firing said first block thyristors in accordance with a first conduction period signal and said first voltage signal; first expanding means for expanding by a first predetermined period an active period of said first conduction period signal from time when said first voltage is substantially zero; second detector means for detecting a second voltage applied across said thyristor switch to generate a second voltage signal when the second block thyristors is forwardly biased; second firing means for firing said second block thyristors in accordance with a second conduction period signal and said second voltage signal; and second expanding means for expanding by a second predetermined period an active period of said second conduction period signal from time when said second voltage is substantially zero; means for generating a first phase signal when said first block thyristors are too be turned on, a second phase signal when said second block thyristors are to be turned on, and an ON signal when said thyristor switched capacitor is to be activated, wherein said first firing means includes first generator means for generating said first conduction period signal when both said first phase signal and said ON signal are generated.

Claim 12

A gate pulse generator according to claim 9, wherein said second firing means includes second generator means for generating said second conduction period signal when both said second phase signal and said ON signal are generated.

Claim 13

A gate pulse generator according to claim 4, wherein said second generator means includes means for terminating the active period of said second conduction period signal, after elapsing said second predetermined period running from a time when both said first and second voltages are substantially zero.

Claim 14

A gate pulse generator according to claim 9, wherein said first generator means includes means for terminating the active period of said first conduction period signal, after elapsing said first predetermined period running from a time when both said first and second voltages are substantially zero.

Claim 15

A gate pulse generator according to claim 9, further comprising: means for generating a first phase signal when said first block of thyristors is to be turned on, a second phase signal when said second block of thyristors is too be turned on, and an ON signal when said thyristor switch capacitor is to be activated; wherein said first expanding means including first delay means for delaying a logical AND of said second phase signal and said ON signal by a first delay time to provide a first delayed signal, first AND means for detecting a first logical AND of said first delayed signal, an inverted logic level of said first voltage signal, and an inverted logic level of said second voltage signal, second delay means for delaying said first logical AND by said first predetermined period too provide a second delayed signal, and a first flip-flop which is set by a logical AND of said first phase signal and said ON signal to activate said first conduction period signal, and which is reset by said second delayed signal to inactivate said first conduction period signal.

Claim 16

A gate pulse generator according to claim 13, wherein said second expanding means includes: third delay means for delaying a logical AND of said first phase signal and said ON signal by a second delay time provide a third delayed signal; second AND means for detecting a second logical AND of said second delayed signal, an inverted logic level of said first voltage signal, and an inverted logic level of said second voltage signal; fourth delay means for delaying said second logical AND by said second predetermined period to provide a fourth delayed signal; and a second flip-flop which is set by a logical AND of said second phase signal and said ON signal to activate said second conduction period signal, and which is reset by said fourth delayed signal to inactivate said second conduction period signal.

Claim 17

A gate pulse generator for a static var compensator comprising a thyristor switch obtained by series-connecting a plurality of antiparallel-connected thyristors, a capacitor ON/OFF-controlled by said thyristor switch, and a reactor series-connected to said capacitor, comprising: flip-flop means, being set by a first phase signal having a predetermined phase difference from a voltage applied to said static var compensator, for providing an output signal, said flip-flop means being reset by an output from a conduction detector of the thyristors operated during a predetermined period starting from the generation of a second phase signal which is generated in a phase opposite to the first phase signal; voltage detecting means for detecting a voltage applied to said thyristor switch to provide a voltage signal; and means for detecting a logical AND of the output signal from said flip-flop means and the voltage signal from said voltage detecting means, and for applying a gate pulse having a predetermined width to the thyristors constituting said thyristor switch when the detected logical AND is set at "1".

Claim 18

A gate pulse generator for a static var compensator comprising a thyristor switch obtained by series-connecting a plurality of antiparallel-connected thyristors, a capacitor ON/OFF-controlled by said thyristor switch, and a reactor series-connected to said capacitor, comprising: flip-flop means, being set by a first phase signal having a predetermined phase difference from a voltage applied to said static var compensator, for providing an output signal, said flip-flop means being reset by an output from a conduction detector of the thyristors operated during a predetermined period starting from the generation of a second phase signal which is generated in a phase opposite to the first phase signal; voltage detecting means for detecting a voltage applied to said thyristor switch to provide a voltage signal; and means for detecting a logical AND of the output signal from said flip-flop means and the voltage signal from said voltage detecting means, and for applying a gate pulse having a predetermined width to the thyristors constituting said thyristor switch when the detected logical AND is set at "1".