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US5093587A Expired / Lapsed US ⏱️ 0.0 years remaining

ECL bidirectional bus for use in a network with modules which employs high resistance interconnect technology between module

Assignee: Unisys Corp
•
Filing: 1990-10-16
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Granted: 1992-03-03
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Expires: 2010-10-16
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Abstract

Abstract ECL bus driver circuits for multi-driver net use are provided with a disable transistor that has its emitter coupled to the emitter of the pull-down transistor of the driver so that when the disable circuit of a driver is activated, the coupled pull-down transistor is not able to sustain current flow through its collector-emitter path, and when the disable transistor is turned off, the pull-down transistor enables the drive circuit to function in its normal manner.

Inventors

  • 👤 Terry B. Zbinden

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 03:21
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/08

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 238 words
In an electronic network comprising a plurality of receivers, a plurality of drivers and a plurality of interconnect lines for coupling signals between said receivers and drivers, the improvement comprising, a) drivers which are constructed with emitter-coupled-logic bipolar technology, each of which drivers comprise 1) an output transistor that has a base coupled to receive a drive signal, a collector coupled to a first voltage source and an emitter coupled to one of said interconnect lines, 2) a pull-down transistor that has a base coupled to a reference voltage, its collector coupled to the emitter of said output transistor and an emitter, and 3) a disable transistor that has a base coupled to receive a disable signal which drives said disable transistor into conduction when said disable signal is at an active level and an emitter coupled to the emitter of said pull-down transistor, b) a pull-down resistor coupled between said junction point and a second voltage source, and c) disable signal generator means for supplying said disable signals to said disable transistors in a manner such that all of said disable transistors except one will be turned on at a given time, wherein said disable transistors are biased so that when they are turned on they will supply sufficient current to the pull-down resistor to which they are coupled to maintain the pull-down transistor which is also coupled to said pull-down resistor in a substantially cut-off state.
Claim 2
Dependent Claim 238 words
In an electronic network comprising a plurality of receivers, a plurality of drivers and a plurality of interconnect lines for coupling signals between said receivers and drivers, the improvement comprising, a) drivers which are constructed with emitter-coupled-logic bipolar technology, each of which drivers comprise 1) an output transistor that has a base coupled to receive a drive signal, a collector coupled to a first voltage source and an emitter coupled to one of said interconnect lines, 2) a pull-down transistor that has a base coupled to a reference voltage, its collector coupled to the emitter of said output transistor and an emitter, and 3) a disable transistor that has a base coupled to receive a disable signal which drives said disable transistor into conduction when said disable signal is at an active level and an emitter coupled to the emitter of said pull-down transistor, b) a pull-down resistor coupled between said junction point and a second voltage source, and c) disable signal generator means for supplying said disable signals to said disable transistors in a manner such that all of said disable transistors except one will be turned on at a given time, wherein said disable transistors are biased so that when they are turned on they will supply sufficient current to the pull-down resistor to which they are coupled to maintain the pull-down transistor which is also coupled to said pull-down resistor in a substantially cut-off state.
Claim 3
Dependent Claim 26 words
In an electronic network as claimed in claim 1 the improvement wherein said interconnect lines have resistance of at least 0.4 ohms per centimeter of length.

References Cited (Backward Citations)

US4236087A Cited
US4347446A Cited
US4577125A Cited
US4874970A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1995-03-03 1995-09-02 1996-03-03 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1999-03-03 1999-09-02 2000-03-03 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2003-03-03 2003-09-02 2004-03-03 $7700.00 Window Closed / Lapsed

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