High speed multiplex switch circuit and method

Claim 2

A high speed, high current analog switching circuit, comprising in combination: (a) a switch JFET having first and second current-carrying electrodes and a gate electrode, the first and second current-carrying electrodes being coupled to an analog input terminal and an analog output terminal, respectively; (b) a first JFET having a source electrode, a drain electrode coupled to a first supply voltage conductor, and a gate electrode coupled to the first current-carrying electrode of the switch JFET; (c) a second JFET having a first current-carrying electrode coupled to the source electrode of the first JFET, a second current-carrying electrode coupled to the gate electrode of the switch JFET, and a gate electrode coupled to the gate electrode of the switch JFET; (d) a third JFET having a source electrode, a drain electrode coupled to the first supply voltage conductor, and a gate electrode coupled to the second current-carrying electrode of the switch JFET; and (e) a fourth JFET having a first current-carrying electrode coupled to the source electrode of the third JFET, a second current-carrying electrode coupled to the gate electrode of the switch JFET, and a gate electrode coupled to the gate electrode of the switch JFET, wherein both rapid turn-on of the switch JFET and rapid equalization of voltages on the analog input terminal and the analog output terminal to within a predetermined minute voltage difference are achieved.

Claim 3

The high speed, high current analog switching circuit of claim 1 wherein the switch JFET is a P-channel JFET, and the first, second, third, and fourth JFETs are P-channel JFETs.

Claim 4

The circuit of claim 2 wherein the switch JFET has a relatively large channel width-to-length ratio, the first and third JFETS each have a channel width-to-length ratio substantially smaller than that of the switch JFET, and the second and fourth JFETs each have a channel width-to-length ratio smaller than that of the first and third JFETs.

Claim 5

The high speed, high current analog switching circuit of claim 2 including a fifth JFET having a source electrode and a gate electrode coupled to a second supply voltage conductor and a drain electrode coupled to the gate electrode of the switch JFET, for performing the function of reducing a source-to-gate voltage of the switch JFET.

Claim 6

The high speed, high current analog switching circuit of claim 4 including a sixth JFET having a source electrode and a gate electrode coupled to the second supply voltage conductor and a drain electrode coupled to the source electrode of the first JFET, and a seventh JFET having a source electrode and a gate electrode coupled to the second supply voltage conductor and a drain electrode coupled to the source electrode of the third JFET.

Claim 7

The high speed, high current analog switching circuit of claim 2 including a control circuit having an output coupled to the gate electrode of the switch JFET, the control circuit including: (1) a current source responsive to a sample control input signal; (2) a transistor having a base electrode coupled to the current source and an emitter electrode coupled to the output of the control circuit; (3) a resistor coupled between the base and emitter electrodes of the transistor, the current source producing a sufficiently large current in response to a first level of the sample control input signal to turn the transistor on, the current source producing essentially zero current in response to a second level of the sample control input signal, whereby rapid turn-off of the switch JFET is achieved in response to the first level and a high impedance condition of the output of the control circuit is achieved in response to the second level.

Claim 8

A high speed, high current analog switching circuit, comprising in combination: (a) a switch JFET having first and second current-carrying electrodes and a gate electrode, the first and second current-carrying electrodes being coupled to an analog input terminal and an analog output terminal, respectively; (b) a first buffer circuit having an input terminal coupled to the analog input terminal, and an output terminal; (c) a first JFET having a first current-carrying electrode coupled to the output terminal of the first buffer circuit, a second current-carrying electrode coupled to the gate electrode of the switch JFET, and a gate electrode coupled to the gate electrode of the switch JFET; (d) a second buffer circuit having an input terminal coupled to the analog output terminal, and an output terminal; and (e) a second JFET having a first current-carrying electrode coupled to the output terminal of the second buffer circuit, a second current-carrying electrode coupled to the gate electrode of the switch JFET, and a gate electrode coupled to the gate electrode of the switch JFET, wherein both rapid turn-on of the switch JFET and rapid equalization of voltages on the analog input terminal and the analog output terminal to within a predetermined minute voltage difference ar achieved.

Claim 9

A high speed, high current analog switching circuit, comprising in combination: (a) a switch JFET having first and second current-carrying electrodes and a gate electrode, the first and second current-carrying electrodes being coupled to an analog input terminal and an analog output terminal, respectively; (b) a first buffer circuit having an input terminal coupled to the analog input terminal, and an output terminal; (c) a first JFET having a first current-carrying electrode coupled to the output terminal of the first buffer circuit, a second current-carrying electrode coupled to the gate electrode of the switch JFET, and a gate electrode coupled to the gate electrode of the switch JFET; (d) a second buffer circuit having an input terminal coupled to the analog output terminal, and an output terminal; and (e) a second JFET having a first current-carrying electrode coupled to the output terminal of the second buffer circuit, a second current-carrying electrode coupled to the gate electrode of the switch JFET, and a gate electrode coupled to the gate electrode of the switch JFET, wherein both rapid turn-on of the switch JFET and rapid equalization of voltages on the analog input terminal and the analog output terminal to within a predetermined minute voltage difference ar achieved.

Claim 12

The method of claim 8 wherein step (d) includes presenting a very high impedance to the gate electrodes of the switch JFET and the first and second JFETs.

Claim 13

The method of claim 8 including preventing forward biasing the source-gate PN junction enough that equalization of the voltages of the input and output terminals through the channel resistance to within approximately 10 microvolts requires no more than approximately 5 microseconds.

Claim 14

The method of claim 10 including preventing forward biasing of the source-gate PN junction by more than approximately 0.2 volts.

Claim 15

An analog switch circuit including circuitry for rapidly equalizing an output voltage produced on an analog output terminal of the analog switch circuit with an input voltage applied to an analog input terminal thereof, the analog switch circuit comprising in combination: (a) a switch JFET, a first JFET, and a second JFET each having first and second current-carrying electrodes and a gate electrode; (b) first and second buffer circuits each having an input and an output; (c) means for applying the input voltage to the first current-carrying electrode of the switch JFET and to the input of the first buffer circuit, the second current-carrying electrode of the switch JFET being coupled to the analog output terminal; (d) means for applying an output signal produced on the output of the first buffer to the first current-carrying electrode of the first JFET, the second current-carrying electrode of the first JFET being coupled to the gate electrode of the switch JFET; (e) means for applying the output voltage to the input of the second buffer circuit and applying an output signal produced on the output of the second buffer circuit to the first current-carrying electrode of the second JFET, the second current-carrying electrode of the second JFET being coupled to the gate electrode of the switch JFET; (f) means for applying a turn-on signal to the gate electrodes of the switch JFET and the first and second JFETs, wherein the first JFET operates in a current saturation mode, the second JFET operates in a resistive mode, and the switch JFET operates in a resistive mode to prevent overcharging a charge storage capacitance of a source-gate PN junction of the switch JFET, preventing slow discharge of the capacitance through a channel resistance of the switch JFET.

Claim 16

An analog switch circuit including circuitry for rapidly equalizing an output voltage produced on an analog output terminal of the analog switch circuit with an input voltage applied to an analog input terminal thereof, the analog switch circuit comprising in combination: (a) a switch JFET, a first JFET, and a second JFET each having first and second current-carrying electrodes and a gate electrode; (b) first and second buffer circuits each having an input and an output; (c) means for applying the input voltage to the first current-carrying electrode of the switch JFET and to the input of the first buffer circuit, the second current-carrying electrode of the switch JFET being coupled to the analog output terminal; (d) means for applying an output signal produced on the output of the first buffer to the first current-carrying electrode of the first JFET, the second current-carrying electrode of the first JFET being coupled to the gate electrode of the switch JFET; (e) means for applying the output voltage to the input of the second buffer circuit and applying an output signal produced on the output of the second buffer circuit to the first current-carrying electrode of the second JFET, the second current-carrying electrode of the second JFET being coupled to the gate electrode of the switch JFET; (f) means for applying a turn-on signal to the gate electrodes of the switch JFET and the first and second JFETs, wherein the first JFET operates in a current saturation mode, the second JFET operates in a resistive mode, and the switch JFET operates in a resistive mode to prevent overcharging a charge storage capacitance of a source-gate PN junction of the switch JFET, preventing slow discharge of the capacitance through a channel resistance of the switch JFET.

Claim 17

The analog switch circuit of claim 12 including means for presenting a high impedance to the gate electrodes of the switch JFET and the first and second JFETs while maintaining them in a turned on condition.

Claim 18

The analog switch circuit of claim 12 including means for preventing forward biasing of the source-gate PN junction enough that equalization of the voltages of the input and output terminals through the channel resistance to within approximately 10 microvolts requires no more than approximately 5 microseconds.

Claim 19

The analog switch circuit of claim 14 including means for preventing forward biasing of the source-gate PN junction by more than approximately 0.2 volts.