Dual channel ionization counter

Claim 1

An event counter comprising a source of counts, first and second counters receiving counts from said source, each counter comprising input gate means operable to cut off counts from said source and means to reset the counter, and each counter also being associated with a latch having first control means selectively enabled to receive a count state from the counter and to hold said count state, and second control means selectively enabled to present said count state to an output, an output bus connected to the outputs of both latches, and a clock generator for generating symmetrical square wave outputs of opposite phases and a predetermined periodicity much greater than that of events to be counted, said outputs of opposite phase being applied to said input gate means of the two counters and to the second control means of their associated latches so that counting of one counter is enabled while a previous count state of that counter held by the associated latch is presented to the output bus, whilst counting of the other counter is disabled, said clock generator further generating control signals delayed relative to transitions of said square wave signal firstly to enable said first control means of a latch associated with that counter whose counting is disabled to receive the count state from that counter, and secondly to enable said means to reset that counter.