US5089869A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Panasonic Holdings Corp
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Filing: 1990-08-07
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Granted: 1992-02-18
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Expires: 2010-08-07
Abstract
Abstract Disclosed is a semiconductor memory device comprising a semiconductor substrate on which memory cells are formed, each including a switching transistor formed on the semiconductor substrate and a capacitor disposed above the switching transistor. The capacitor has a storage electrode, a cell plate and a capacitor insulating film sandwiched therebetween. The storage electrodes of at least two adjacent memory cells are partly disposed one above the other, with part of the cell plate interposed therebetween. Also disclosed is a semiconductor memory device in which the capacitors of the memory cells are disposed in a trench formed in the semiconductor substrate. The two switching transistors of two adjacent memory cells are located on each island-shaped active region surrounded by the trench. The storage electrodes of the capacitors of the two adjacent memory cells extend side by side around the corresponding active region, with part of the cell plate interposed between the storage electrodes.
Inventors
- 👤 Naoto Matsuo
- 👤 Shozo Okada
- 👤 Michihiro Inoue
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:17
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10B12/318
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
117 words
A semiconductor memory device comprising: a semiconductor substrate having a plurality of active regions electrically isolated from one another; and a plurality of memory cells formed on said semiconductor substrate, each of which has a switching transistor formed on the corresponding active region, and a capacitor disposed above said switching transistor, said capacitor having a storage electrode, a cell plate, and a capacitor insulating film interposed therebetween, said storage electrode being connected to said switching transistor, and said cell plate being common to all the memory cells on said semiconductor substrate; wherein the storage electrodes of at least two adjacent memory cells are partly disposed one above the other with part of said cell plate interposed therebetween.
Claim 2
Dependent Claim
117 words
A semiconductor memory device comprising: a semiconductor substrate having a plurality of active regions electrically isolated from one another; and a plurality of memory cells formed on said semiconductor substrate, each of which has a switching transistor formed on the corresponding active region, and a capacitor disposed above said switching transistor, said capacitor having a storage electrode, a cell plate, and a capacitor insulating film interposed therebetween, said storage electrode being connected to said switching transistor, and said cell plate being common to all the memory cells on said semiconductor substrate; wherein the storage electrodes of at least two adjacent memory cells are partly disposed one above the other with part of said cell plate interposed therebetween.
Claim 3
Dependent Claim
36 words
A semiconductor memory device according to claim 1, wherein the switching transistors which are respectively connected to the two storage electrodes partly disposed one above the other are both placed in one of said active regions.
Claim 4
Dependent Claim
34 words
A semiconductor memory device according to claim 1, wherein the switching transistors which are respectively connected to the two storage electrodes partly disposed one above the other are placed in two different active regions.
Claim 5
Dependent Claim
175 words
A semiconductor memory device comprising: a semiconductor substrate having a trench formed therein and a plurality of island-shaped active regions electrically isolated from one another by said trench; and a plurality of memory cells formed on said semiconductor substrate, each of which has a switching transistor formed on the corresponding island-shaped active region, and a capacitor disposed within said trench, said capacitor having a storage electrode, a cell plate, and a capacitor insulating film interposed therebetween, said storage electrode being connected to said switching transistor, and said cell plate being common to all the capacitors in said trench; wherein the switching transistors of two adjacent memory cells are formed on each island-shaped active region, and the two storage electrodes respectively connected to said switching transistors of said two adjacent memory cells extend side by side around the sides of said island-shaped active region, with part of said cell plate interposed between said two storage electrodes and with an insulating film interposed between said island-shaped active region and the inner one of said two storage electrodes.
Claim 6
Dependent Claim
175 words
A semiconductor memory device comprising: a semiconductor substrate having a trench formed therein and a plurality of island-shaped active regions electrically isolated from one another by said trench; and a plurality of memory cells formed on said semiconductor substrate, each of which has a switching transistor formed on the corresponding island-shaped active region, and a capacitor disposed within said trench, said capacitor having a storage electrode, a cell plate, and a capacitor insulating film interposed therebetween, said storage electrode being connected to said switching transistor, and said cell plate being common to all the capacitors in said trench; wherein the switching transistors of two adjacent memory cells are formed on each island-shaped active region, and the two storage electrodes respectively connected to said switching transistors of said two adjacent memory cells extend side by side around the sides of said island-shaped active region, with part of said cell plate interposed between said two storage electrodes and with an insulating film interposed between said island-shaped active region and the inner one of said two storage electrodes.
References Cited (Backward Citations)
US4958318A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-02-17 | 1995-08-19 | 1996-02-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-02-17 | 1999-08-19 | 2000-02-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-02-17 | 2003-08-19 | 2004-02-18 | $7700.00 | Window Closed / Lapsed |