Interrogation signal processor for air traffic control communications

Claim 2

A digital Mode S Interrogation Signal Processor for implementation in either a Mode S transponder or air collision avoidance system, comprising: Mode S preamble detector means for detecting a Mode S preamble of a transmitted signal and for generating a preamble detection signal; phase-shift reversal detection means, in response to said preamble detection signal, for detecting a phase shift reversal in the transmitted signal and for generating a Mode S verification signal; and said phase-shift reversal detection means determining that the transmitted signal is a Mode S signal when generating said Mode S verification signal; digital differential phase-shift keyed demodulating means, in response to said Mode S verification signal, or digitally demodulating said Mode S signal to obtain useful information for air collision avoidance.

Claim 3

The digital Mode S Interrogation Signal Processor as claimed in claim 1, wherein said digital differential phase-shift keyed demodulating means comprises: splitter means for splitting said Mode S signal into a quadrature signal and an in-phase signal, said quadrature signal being odd samples of said Mode S signal and said in-phase signal being even samples of said Mode S signal; digital Hilbert transformation means, operatively connected to said splitter means, for performing a Hilbert transformation upon said quadrature signal and said in-phase signal to produce transformed signals; delay means, operatively connected to said digital Hilbert transformation means, for delaying the transformed quadrature and in-phase signals by one clock cycle; multiplying means, operatively connected to said delay means, for multiplying the delayed transformed quadrature signal with a current transformed quadrature signal and for multiplying the delayed transformed in-phase signal by a current transformed in-phase signal; summer means, operatively connected to said multiplying means, for summing the products produced by said multiplying means; and threshold means, operatively connected to said summer means, for determining a polarity of the sum produced by said summer means.

Claim 4

The digital Mode S Interrogation Signal Processor as claimed in claim 2, wherein said digital Hilbert transform means comprises: Hilbert delay means, operatively connected to said splitter means, for delaying said quadrature signal and said in-phase signal by one clock cycle; first subtractor means, operatively connected to said Hilbert delay means and said delay means, for subtracting a current quadrature signal from the delayed quadrature signal to produce the transformed quadrature signal; and second subtractor means, operatively connected to said Hilbert delay means and said delay means, for subtracting a current in-phase signal from the delayed in-phase signal to produce the transformed in-phase signal.

Claim 5

The digital Mode S Interrogation Signal Processor as claimed in claim 2, wherein said threshold means produce data having a logic "1" when said polarity is positive and a logic "0" when said polarity is negative.

Claim 6

The digital Mode S Interrogation Signal Processor as claimed in claim 1, further comprising: clock means, operatively connected to said phase shift reversal detector means and said digital differential phase shift keyed demodulator means, for producing a clock signal for said digital differential phase shift keyed demodulator in response to the detected phase shift reversal.

Claim 7

The digital Mode S Interrogation Signal Processor as claimed in claim 5, wherein said clock means produces a clock signal having a frequency of 16 MHz during a digital demodulation process.

Claim 8

The digital Mode S Interrogation Signal Processor as claimed in claim 1, wherein said Mode S preamble detector comprises: comparator means, for comparing a voltage level of the transmitted Mode S signal with a reference threshold level to produce a pulse when said voltage level exceeds said reference threshold level; and correlator means, operatively connected to said comparator means, for determining if said comparator means has produced two pulses and if said two pulses are separated by predetermined time gap; said correlator means, producing preamble detection signal when said two pulses are present and are separated by said predetermined time gap.

Claim 9

The digital Mode S Interrogation Signal Processor as claimed in claim 7, wherein said reference threshold level is programmable.

Claim 10

The digital Mode S Interrogation Signal Processor as claimed in claim 4, further comprising: computer means, operatively connected to said threshold means, for receiving serially said data produced by said threshold means and for using said data to avoid collisions with other moving objects.

Claim 11

The digital Mode S Interrogation Signal Processor as claimed in claim 1, further comprising: Mode C means for processing and identifying a Mode C signal.

Claim 12

The digital Mode S Interrogation Signal Processor as claimed in claim 1, further comprising: Mode A means for processing and identifying a Mode A signal.

Claim 13

The digital Mode S Interrogation Signal Processor as claimed in claim 2, wherein said multiplying means comprises: first multiplying means, operatively connected to said delay means, for multiplying the delayed transformed quadrature signal with a current transformed quadrature signal; second multiplying means, operatively connected to said delay means, for multiplying the delayed transformed in-phase signal with a current in-phase signal; and weighting means, operatively connected to said summer means, said first and said second multiplying means, for arithmatically weighing the products from said first and second multiplying means such that middle samples of the transmitted signal are given greater weight, thereby avoiding interference at either edge of a passband of said Mode S signal.

Claim 14

The digital Mode S Interrogation Signal Processor as claimed in claim 12, wherein eight samples of the transmitted signal produce one bit of data.

Claim 15

The digital Mode S Interrogation Signal Processor as claimed in claim 1, wherein said digital differential phase-shift keyed demodulating means comprises: splitter means for splitting said Mode S signal into a quadrature signal and an in-phase signal, said quadrature signal being odd samples of said Mode S signal and said in-phase signal being even samples of said Mode S signal; digital Hilbert transformation means, operatively connected to said splitter means, for performing a Hilbert transformation upon said quadrature signal and said in-phase signal to produce transformed signals; delay means, operatively connected to said digital Hilbert transformation means, for delaying the transformed quadrature and in-phase signals by one clock cycle; multiplying means, operatively connected to said delay means, for multiplying the delayed transformed quadrature signal with a current transformed quadrature signal and for multiplying the delayed transformed in-phase signal by a current transformed in-phase signal; weighting means, operatively connected to said multiplying means, for arithmatically weighing the products from said multiplying means such that middle samples of the transmitted signal are given greater weight; first summer means, operatively connected to said multiplying means, for summing the products produced by said multiplying means; second summer means, operatively connected to said weighting means, for summing the weighted products produced by said weighting means; switch means, operatively connected to said first and second summer means, for selecting a sum from either said first or second summer means in accordance with a type of noise and interference present in the transmitted signal; and threshold means, operatively connected to said switch means, for determining a polarity of the selected sum from said switch means.

Claim 16

The digital Mode S Interrogation Signal Processor as claimed in claim 14, wherein eight samples of the transmitted signal produce one bit of data.

Claim 17

A Mode S Interrogation Signal Processor for collision avoidance system, comprising: Mode S signal detector means for determining if a received signal is a Mode S signal; splitter means, operatively connected to said Mode S signal detector means, for splitting a transmitted Mode S signal into a quadrature signal and an in-phase signal, said quadrature signal being odd-samples of said transmitted Mode S signal and said in-phase signal being even samples of said transmitted Mode S. signal; digital Hilbert transformation means, operatively connected to said splitter means, for performing a Hilbert transformation upon said quadrature signal and said in-phase signal to produce transformed signals; delay means, operatively connected to said digital Hilbert transformation means, for delaying the transformed quadrature and in-phase signals by one clock cycle; multiplying means, operatively connected to said delay means, for multiplying the delayed transformed quadrature signal with a current transformed quadrature signal and for multiplying the delayed transformed in-phase signal by a current transformed in-phase signal; summer means, operatively connected to said multiplying means, for summing the products produced by said multiplying means; and threshold means, operatively connected to said summer means, for determining a polarity of the sum produced by said summer means.

Claim 18

A Mode S Interrogation Signal Processor for collision avoidance system, comprising: Mode S signal detector means for determining if a received signal is a Mode S signal; splitter means, operatively connected to said Mode S signal detector means, for splitting a transmitted Mode S signal into a quadrature signal and an in-phase signal, said quadrature signal being odd-samples of said transmitted Mode S signal and said in-phase signal being even samples of said transmitted Mode S. signal; digital Hilbert transformation means, operatively connected to said splitter means, for performing a Hilbert transformation upon said quadrature signal and said in-phase signal to produce transformed signals; delay means, operatively connected to said digital Hilbert transformation means, for delaying the transformed quadrature and in-phase signals by one clock cycle; multiplying means, operatively connected to said delay means, for multiplying the delayed transformed quadrature signal with a current transformed quadrature signal and for multiplying the delayed transformed in-phase signal by a current transformed in-phase signal; summer means, operatively connected to said multiplying means, for summing the products produced by said multiplying means; and threshold means, operatively connected to said summer means, for determining a polarity of the sum produced by said summer means.

Claim 19

The digital Mode S Interrogation Signal Processor as claimed in claim 16, wherein said threshold means produce data having a logic "1" when said polarity is positive and a logic "0" when said polarity is negative.

Claim 20

The Mode S Interrogation Signal Processor as claimed in claim 16, wherein said digital Hilbert transform means comprises: Hilbert delay means, operatively connected to said splitter means, for delaying said quadrature signal and said in-phase signal by one clock cycle; first subtractor means, operatively connected to said Hilbert delay means and said delay means, for subtracting a current quadrature signal from the delayed quadrature signal to produce the transformed quadrature signal; and second subtractor means, operatively connected to said Hilbert delay means and said delay means, for subtracting a current in-phase signal from the delayed in-phase signal to produce the transformed in-phase signal.

Claim 21

The Mode S Interrogation Signal Processor as claimed in claim 16, wherein said Mode S signal detector means comprises: comparator means, for comparing a voltage level of the transmitted signal with a threshold level to produce a pulse when said voltage level exceeds said threshold level; and correlator means, operatively connected to said comparator means, for determining if said comparator means has produced two pulses and if said two pulses are separated by predetermined time gap; said correlator means, producing a preamble detector signal when said two pulses are present and are separated by said predetermined time gap, thereby indicating that a Mode S signal is being received.

Claim 22

The Mode S Interrogation Signal processor as claimed in claim 16, further comprising: computer means, operatively connected to said threshold means, for receiving serially said data produced by said threshold means and for using said data to avoid collisions with other moving objects.

Claim 23

The Mode S Interrogation Signal Processor as claimed in claim 16, further comprising: Mode C means for processing and identifying a Mode C signal.

Claim 24

The Mode S Interrogation Signal Processor as claimed in claim 16, further comprising: Mode A means for processing and identifying a Mode A signal.

Claim 25

The Mode S Interrogation Signal Processor as claimed in claim 16, wherein said multiplying means comprises: first multiplying means, operatively connected to said delay means, for multiplying the delayed transformed quadrature signal with a current transformed quadrature signal; second multiplying means, operatively connected to said delay means, for multiplying the delayed transformed in-phase signal with a current in-phase signal; and weighting means, operatively connected to said summer means, said first multiplying means and said second multiplying means, for arithmatically weighing the products from said first and second multiplying means such that middle samples of the transmitted signal are given greater weight, thereby avoiding interference at either edge of a passband of said Mode S signal.

Claim 26

The digital Mode S Interrogation Signal Processor as claimed in claim 23, wherein eight samples of the said Mode S signal produce one bit of data.

Claim 27

A Mode S Interrogation Signal Processor for collision avoidance system, comprising: splitter means, operatively connected to said Mode S signal detector means, for splitting a transmitted Mode S signal into a quadrature signal and an in-phase signal, said quadrature signal being odd-samples of said Mode S signal and said in-phase signal being even samples of said Mode S signal; digital Hilbert transformation means, operatively connected to said splitter means, for performing a Hilbert transformation upon said quadrature signal and said in-phase signal to produce transformed signals; delay means, operatively connected to said digital Hilbert transformation means, for delaying the transformed quadrature and in-phase signals by one clock cycle; multiplying means, operatively connected to said delay means, for multiplying the delayed transformed quadrature signal with a current transformed quadrature signal and for multiplying the delayed transformed in-phase signal by a current transformed in-phase signal; weighting means, operatively connected to said multiplying means, for arithmatically weighing the products from said multiplying means such that middle samples of the transmitted signal are given greater weight; first summer means, operatively connected to said multiplying means, for summing the products produced by said multiplying means; second summer means, operatively connected to said weighting means, for summing the weighted products produced by said weighting means; switch means, operatively connected to said first and second summer means, for selecting a sum from either said first or second summer means in accordance with a type of noise and interference present in the transmitted signal; and threshold means, operatively connected to said switch means, for determining a polarity of the selected sum from said switch means.

Claim 28

A Mode S Interrogation Signal Processor for collision avoidance system, comprising: splitter means, operatively connected to said Mode S signal detector means, for splitting a transmitted Mode S signal into a quadrature signal and an in-phase signal, said quadrature signal being odd-samples of said Mode S signal and said in-phase signal being even samples of said Mode S signal; digital Hilbert transformation means, operatively connected to said splitter means, for performing a Hilbert transformation upon said quadrature signal and said in-phase signal to produce transformed signals; delay means, operatively connected to said digital Hilbert transformation means, for delaying the transformed quadrature and in-phase signals by one clock cycle; multiplying means, operatively connected to said delay means, for multiplying the delayed transformed quadrature signal with a current transformed quadrature signal and for multiplying the delayed transformed in-phase signal by a current transformed in-phase signal; weighting means, operatively connected to said multiplying means, for arithmatically weighing the products from said multiplying means such that middle samples of the transmitted signal are given greater weight; first summer means, operatively connected to said multiplying means, for summing the products produced by said multiplying means; second summer means, operatively connected to said weighting means, for summing the weighted products produced by said weighting means; switch means, operatively connected to said first and second summer means, for selecting a sum from either said first or second summer means in accordance with a type of noise and interference present in the transmitted signal; and threshold means, operatively connected to said switch means, for determining a polarity of the selected sum from said switch means.

Claim 29

The digital Mode S Interrogation Signal Processor as claimed in claim 25, wherein eight samples of the transmitted signal produce one bit of data.

Claim 30

The Mode S Interrogation Signal Processor as claimed in claim 25, wherein said digital Hilbert transform means comprises: Hilbert delay means, operatively connected to said splitter means, for delaying said quadrature signal and said in-phase signal by one clock cycle; first subtractor means, operatively connected to said Hilbert delay means and said delay means, for subtracting a current quadrature signal from the delayed quadrature signal to produce the transformed quadrature signal; and second subtractor means, operatively connected to said Hilbert delay means and said delay means, for subtracting a current in-phase signal from the delayed in-phase signal to produce the transformed in-phase signal.

Claim 31

The Mode S Interrogation Signal Processor as claimed in claim 25, wherein said Mode S signal detector means comprises: comparator means, for comparing a voltage level of the transmitted signal with a threshold level to produce a pulse when said voltage level exceeds said threshold level; and correlator means, operatively connected to said comparator means, for determining if said comparator means has produced two pulses and if said two pulses are separated by predetermined time gap; said correlator means, producing a preamble detection signal when said two pulses are present and are separated by said predetermined time gap, thereby indicating that a Mode S signal is being received.

Claim 32

The Mode S Interrogation Signal Processor as claimed in claim 25, further comprising: computer means, operatively connected to said threshold means, for receiving serially said data produced by said threshold means and for using said data to avoid collisions with other moving objects.

Claim 33

The Mode S Interrogation Signal Processor as claimed in claim 25, further comprising: Mode C means for processing and identifying a Mode C signal.

Claim 34

The Mode S Interrogation Signal Processor as claimed in claim 25, further comprising: Mode A means for processing and identifying a Mode A signal.

Claim 35

The Mode S Interrogation Signal Processor as claimed in claim 28, wherein said threshold level is programmable.

Claim 36

A digital Mode S uplink demodulator for demodulating a received Mode S signal, comprising: phase splitting means, for splitting the received Mode S signal into an in-phase signal and a quadrature signal; digital Hilbert transformation means, operatively connected to said phase splitting means, for performing a Hilbert transformation upon said in-phase signal and said quadrature signal to produce transformed signals; delay means, operatively connected to said digital Hilbert transformation means, for delaying the transformed quadrature and in-phase signals by one clock cycle; multiplying means, operatively connected to said delay means, for multiplying the delayed transformed quadrature signal with a current transformed quadrature signal and for multiplying the delayed transformed in-phase signal by a current transformed in-phase signal; summer means, operatively connected to said multiplying means, for summing the products produced by said multiplying means; and threshold means, operatively connected to said summer means, for determining a polarity of the sum produced by said summer means.

Claim 37

A digital Mode S uplink demodulator for demodulating a received Mode S signal, comprising: phase splitting means, for splitting the received Mode S signal into an in-phase signal and a quadrature signal; digital Hilbert transformation means, operatively connected to said phase splitting means, for performing a Hilbert transformation upon said in-phase signal and said quadrature signal to produce transformed signals; delay means, operatively connected to said digital Hilbert transformation means, for delaying the transformed quadrature and in-phase signals by one clock cycle; multiplying means, operatively connected to said delay means, for multiplying the delayed transformed quadrature signal with a current transformed quadrature signal and for multiplying the delayed transformed in-phase signal by a current transformed in-phase signal; summer means, operatively connected to said multiplying means, for summing the products produced by said multiplying means; and threshold means, operatively connected to said summer means, for determining a polarity of the sum produced by said summer means.

Claim 38

The digital Mode S uplink demodulator as claimed in claim 33, wherein said threshold means produce data having a logic "1" when said polarity is positive and a logic "0" when said polarity is negative.

Claim 39

The digital Mode S uplink demodulator as claimed in claim 33, wherein said digital Hilbert transform means comprises: Hilbert delay means, operatively connected to said splitter means, for delaying said quadrature signal and said in-phase signal by one clock cycle; first subtractor means, operatively connected to said Hilbert delay means and said delay means, for subtracting a current quadrature signal from the delayed quadrature signal to produce the transformed quadrature signal; and second subtractor means, operatively connected to said Hilbert delay means and said delay means, for subtracting a current in-phase signal from the delayed in-phase signal to produce the transformed in-phase signal.

Claim 40

The digital Mode S uplink demodulator as claimed in claim 33, wherein said multiplying means comprises: first multiplying means, operatively connected to said delay means, for multiplying the delayed transformed quadrature signal with a current transformed quadrature signal; second multiplying means, operatively connected to said delay means, for multiplying the delayed transformed in-phase signal with a current in-phase signal; and weighting means, operatively connected to said summer means, said first multiplying means and said second multiplying means, for arithmatically weighing the products from said first and second multiplying means such that middle samples of the transmitted signal are given greater weight, thereby avoiding interference at either edge of a passband of said Mode S signal.

Claim 41

The diqital Mode S uplink demodulator as olaimed in claim 36, wherein eight samples of the transmitted signal produce one bit of data.

Claim 42

A digital Mode S uplink demodulator for demodulating a received Mode S signal, comprising: phase splitting means, for splitting the received Mode S signal into an in-phase signal and a quadrature signal; digital Hilbert transformation means, operatively connected to said phase splitting means, for performing a Hilbert transformation upon said in-phase signal and said quadrature signal to produce transformed signals; delay means, operatively connected to said digital Hilbert transformation means, for delaying the transformed quadrature and in-phase signals by one clock cycle; multiplying means, operatively connected to said delay means, for multiplying the delayed transformed quadrature signal with a current transformed quadrature signal and for multiplying the delayed transformed in-phase signal by a current transformed in-phase signal; weighting means, operatively connected to said multiplying means, for arithmatically weighing the products from said multiplying means such that middle samples are given greater weight; first summer means, operatively connected to said multiplying means, for summing the products produced by said multiplying means; second summer means, operatively connected to said weighting means, for summing the weighted products produced by said multiplying means; switch means, operatively connected to said first and second summer means, for selecting a sum from either said first or second summer means in accordance with a type of noise or interference present in the transmitted signal; and threshold means, operatively connected to said summer means, for determining a polarity of the sum produced by said summer means.

Claim 43

A digital Mode S uplink demodulator for demodulating a received Mode S signal, comprising: phase splitting means, for splitting the received Mode S signal into an in-phase signal and a quadrature signal; digital Hilbert transformation means, operatively connected to said phase splitting means, for performing a Hilbert transformation upon said in-phase signal and said quadrature signal to produce transformed signals; delay means, operatively connected to said digital Hilbert transformation means, for delaying the transformed quadrature and in-phase signals by one clock cycle; multiplying means, operatively connected to said delay means, for multiplying the delayed transformed quadrature signal with a current transformed quadrature signal and for multiplying the delayed transformed in-phase signal by a current transformed in-phase signal; weighting means, operatively connected to said multiplying means, for arithmatically weighing the products from said multiplying means such that middle samples are given greater weight; first summer means, operatively connected to said multiplying means, for summing the products produced by said multiplying means; second summer means, operatively connected to said weighting means, for summing the weighted products produced by said multiplying means; switch means, operatively connected to said first and second summer means, for selecting a sum from either said first or second summer means in accordance with a type of noise or interference present in the transmitted signal; and threshold means, operatively connected to said summer means, for determining a polarity of the sum produced by said summer means.

Claim 44

The digital Mode S uplink demodulator as claimed in claim 38, wherein said threshold means produce data having a logic "1" when said polarity is positive and a logic "0" when said polarity is negative.

Claim 45

The digital Mode S uplink demodulator as claimed in claim 38, wherein said digital Hilbert transform means comprises: Hilbert delay means, operatively connected to said splitter means, for delaying said quadrature signal and said in-phase signal by one clock cycle; first subtractor means, operatively connected to said Hilbert delay means and said delay means, for subtracting a current quadrature signal from the delayed quadrature signal to produce the transformed quadrature signal; and second subtractor means, operatively connected to said Hilbert delay means and said delay means, for subtracting a current in-phase signal from the delayed in-phase signal to produce the transformed in-phase signal.

Claim 48

The method as claimed in claim 41, wherein said step (a) comprises the steps of: (n) comparing a voltage level of the transmitted Mode S signal with a threshold level; (o) producing a pulse signal when said step (n) determines that the voltage level exceeds the threshold level; (p) determining if said step (o) has produced two pulses which are separated by a predetermined time gap, thereby detecting a preamble of a Mode S signal when said step (o) has produced two pulses separated by the predetermined time gap.

Claim 49

The method as claimed in claim 42, wherein the threshold level is programmable.

Claim 50

The method as claimed in claim 41, wherein said step (f) comprises the steps of: (n) delaying the quadrature signal and the in-phase signal by one clock cycle; (o) subtracting a current quadrature signal from the delayed quadrature signal to produce the transformed quadrature signal; and (p) subtracting a current in-phase signal from the delayed in-phase signal to produce the transformed in-phase signal.

Claim 51

The method as claimed in claim 41, wherein the products of said steps (h) and (i) are arithmatically weighted prior to summing in said step (j) such that middle samples of the transmitted signal are given greater weight.

Claim 52

The method as claimed in claim 45, wherein eight samples of the transmitted data produce one bit of data.

Claim 53

The method as claimed in claim 41, further comprising the steps of: (n) weighting arithmatically the products of steps (h) and (i); (o) summing the weight products of said step (n); and (p) selecting either the sum of said step (j) or said step (o) according to a type of noise or interference present in the transmitted signal; said step (k) determining a polarity of the selected sum of said step (p).

Claim 54

The method as claimed in claim 47, wherein said step (a) comprises the steps of: (q) Comparing a voltage level of the transmitted Mode S signal with a reference threshold level; (r) producing a pulse signal when said step (q) determines that the voltage level exceeds the threshold level; (s) determining if said step (r) has produced two pulses which are separated by a predetermined time gap, thereby detecting a preamble of a Mode S signal when said step (r) has produced two pulses separated by the predetermined time gap.

Claim 55

The method as claimed in claim 48, wherein the threshold level is programmable.

Claim 56

The method as claimed in claim 47, wherein said step (f) comprises the steps of: (q) delaying the quadrature signal and the in-phase signal by one clock cycle; (r) subtracting a current quadrature signal from the current quadrature signal to produce the transformed quadrature signal; and (s) subtracting a current in-phase signal from the delayed in-phase signal to produce the transformed in-phase signal.

Claim 59

The method as claimed in claim 51, wherein said step (a) comprises the steps of: (l) comparing a voltage level of the transmitted Mode S signal with a threshold level; (m) producing a pulse signal when said step (l) determines that the voltage level exceeds the threshold level; (n) determining if said step (m) has produced two pulses which are separated by a predetermined time gap, thereby detecting a preamble of a Mode S signal when said step (m) has produced two pulses separated by the predetermined time gap.

Claim 60

The method as claimed in claim 52, wherein the threshold level is programmable.

Claim 61

The method as claimed in claim 51, wherein said step (d) comprises the steps of: (l) delaying the quadrature signal and the in-phase signal by one clock cycle; (m) subtracting a current quadrature signal from the delayed quadrature signal to produce the transformed quadrature signal; and (n) subtracting a current in-phase signal from the delayed in-phase signal to produce the transformed in-phase signal.

Claim 62

The method as claimed in claim 51, wherein the products of said steps (f) and (g) are arithmatically weighted prior to summing in said step (h) such that middle samples of the transmitted signal are given greater weight.

Claim 63

The method as claimed in claim 55, wherein eight samples of the transmitted data produce one bit of data.

Claim 66

The method as claimed in claim 57, wherein said step (a) comprises the steps of: (o) comparing a voltage level of the transmitted Mode S signal with a threshold level; (p) producing a pulse signal when said step (o) determines that the voltage level exceeds the threshold level; (q) determining if said step (p) has produced two pulses which are separated by a predetermined time gap, thereby detecting a preamble of a Mode S signal when said step (p) has produced two pulses separated by the predetermined time gap.

Claim 67

The method as claimed in claim 58, wherein the threshold level is programmable.

Claim 68

The method as claimed in claim 57, wherein said step (d) comprises the steps of: (o) delaying the quadrature signal and the in-phase signal by one clock cycle; (p) subtracting a current quadrature signal from the delayed quadrature signal to produce the transformed quadrature signal; and (q) subtracting a current in-phase signal from the delayed in-phase signal to produce the transformed in-phase signal.

Claim 71

The method as claimed in claim 61, wherein said step (b) comprises the steps of: (j) delaying the quadrature signal and the in-phase signal by one clock cycle; (k) subtracting a current quadrature signal from the delayed quadrature signal to produce the transformed quadrature signal; and (l) subtracting a current in-phase signal from the delayed in-phase signal to produce the transformed in-phase signal.

Claim 72

The method as claimed in claim 61, wherein the products of said steps (d) and (e) are arithmatically weighted prior to summing in said step (f) such that middle samples of the transmitted signal are given greater weight.

Claim 73

The method as claimed in claim 63, wherein eight samples of the transmitted data produce one bit of data.

Claim 76

The method as claimed in claim 65, wherein said step (b) comprises the steps of: (m) delaying the quadrature signal and the in-phase signal by one clock cycle; (n) subtracting a current quadrature signal from the delayed quadrature signal to produce the transformed quadrature signal; and (o) subtracting a current in-phase signal from the delayed in-phase signal to produce the transformed in-phase signal.