Differential amplifier

Claim 2

A differential amplifier comprising: a first differential amplifier for generating first and second differential output signals responsive to first and second input signals, said first differential amplifier comprising at least first and second MOS transistors; a second differential amplifier coupled to said first differential amplifier for generating third and fourth differential output signals responsive to said first and second differential output signals, said second differential amplifier comprising at least third and fourth bipolar transistors; and fifth and sixth transistors driven responsive to said first and second input signals, said fifth and sixth transistors coupled to said first and second transistors to act as loads for said first differential amplifier, wherein said fifth transistor is coupled to said third transistor and said sixth transistor is coupled to said fourth transistor to provide feedback to said second differential amplifier.

Claim 3

The differential amplifier of claim 1 wherein said fifth and sixth transistors are coupled to prevent the collector-base junction of said third and fourth bipolar transistors from becoming forward biased.

Claim 4

The differential amplifier of claim 2 wherein said fifth and sixth transistors comprise MOS transistors driven responsive to said input signals.

Claim 5

The differential amplifier of claim 1 wherein each bipolar transistor has an active load coupled to its collector.

Claim 6

The differential amplifier of claim 4 wherein said active loads each comprise a pair of p-channel transistors forming a current mirror.

Claim 7

A circuit for translating an input signal from a first set of logic levels to a second set of logic levels comprising: a voltage source for providing a reference voltage; a first differential amplifier coupled to the input signal and the reference voltage for generating first and second differential output signals responsive to the voltage differential between the input signal and the reference voltage, said first differential amplifier comprising at least first and second MOS transistors; a second differential amplifier coupled to said first differential amplifier for generating third and fourth differential output signals responsive to said first and second differential output signals, said second differential amplifier comprising at least third and fourth bipolar transistors; and fifth and sixth transistors driven responsive to said first and second input signals, said fifth and sixth transistors coupled to said first and second transistors to act as loads for said first differential amplifier, wherein said fifth transistor is coupled to said third transistor and said sixth transistor is coupled to said fourth transistor to provide feedback to said second differential amplifier.

Claim 8

A circuit for translating an input signal from a first set of logic levels to a second set of logic levels comprising: a voltage source for providing a reference voltage; a first differential amplifier coupled to the input signal and the reference voltage for generating first and second differential output signals responsive to the voltage differential between the input signal and the reference voltage, said first differential amplifier comprising at least first and second MOS transistors; a second differential amplifier coupled to said first differential amplifier for generating third and fourth differential output signals responsive to said first and second differential output signals, said second differential amplifier comprising at least third and fourth bipolar transistors; and fifth and sixth transistors driven responsive to said first and second input signals, said fifth and sixth transistors coupled to said first and second transistors to act as loads for said first differential amplifier, wherein said fifth transistor is coupled to said third transistor and said sixth transistor is coupled to said fourth transistor to provide feedback to said second differential amplifier.

Claim 9

The differential amplifier of claim 6 wherein said fifth and sixth transistors are coupled to prevent the collector-base junction of said bipolar transistors from becoming forward biased.

Claim 10

The differential amplifier of claim 7 wherein said fifth and sixth transistors comprise MOS transistors driven responsive to said input signals.

Claim 11

The differential amplifier of claim 6 wherein each bipolar transistor has an active load coupled to its collector.

Claim 12

The differential amplifier of claim 9 wherein said active loads each comprise a pair of p-channel transistors forming a current mirror.

Claim 15

The method of claim 11 wherein said step of providing feedback comprises the step of preventing the collector-base junctions of the bipolar transistors from becoming forward biased.

Claim 16

The method of claim 12 wherein said preventing step comprises selectively enabling a MOS transistor coupled between the base and collector of each bipolar transistor such that the base voltage remains below the collector voltage.

Claim 17

A differential amplifier for amplifying first and second input signals comprising: first, second, third, fourth, fifth, and sixth transistors; and first and second active loads connected to a voltage source, wherein: said first input signal is connected to control terminals of said first and fourth transistors; said second input signal is connected to control terminals of said second and third transistors; a first terminal of each of said first, second, fifth and sixth transistors are connected to ground; a second terminal of said first transistor is connected to a control terminal of said fifth transistor and to a first terminal of said third transistor; a second terminal of said second transistor is connected to a control terminal of said sixth transistor and to a first terminal of said fourth transistor; a second terminal of said fifth transistor is connected to a second terminal of said third transistor and to said first active load; and a second terminal of said sixth transistor is connected to a second terminal of said fourth transistor and to said second active load.

Claim 18

A differential amplifier for amplifying first and second input signals comprising: first, second, third, fourth, fifth, and sixth transistors; and first and second active loads connected to a voltage source, wherein: said first input signal is connected to control terminals of said first and fourth transistors; said second input signal is connected to control terminals of said second and third transistors; a first terminal of each of said first, second, fifth and sixth transistors are connected to ground; a second terminal of said first transistor is connected to a control terminal of said fifth transistor and to a first terminal of said third transistor; a second terminal of said second transistor is connected to a control terminal of said sixth transistor and to a first terminal of said fourth transistor; a second terminal of said fifth transistor is connected to a second terminal of said third transistor and to said first active load; and a second terminal of said sixth transistor is connected to a second terminal of said fourth transistor and to said second active load.

Claim 19

The differential amplifier of claim 14 wherein said active loads comprise a pair of p-channel transistors forming a current mirror.

Claim 20

The amplifier of claim 14 wherein said first and second transistors are MOS transistors and wherein said first terminal is the source, said second terminal is the drain, and said control terminal is the gate.

Claim 21

The amplifier of claim 14 wherein said third and fourth transistors are MOS transistors and wherein said first terminal is the source, said second terminal is the drain, and said control terminal is the gate.

Claim 22

The amplifier of claim 14 wherein said fifth and sixth transistors are bipolar transistors and wherein said first terminal is the emitter, said second terminal is the collector, and said control terminal is the base.