Method for managing a data cache using virtual external storage addresses as arguments

Claim 2

A CPU implemented method for managing a cache for external storage having a first and second page organized files including a data file versioning feature, said CPU including internal storage formed from RAM addressable pages and external storage formed from DASD addressable pages, comprising the steps of: (a) creating at least two named pages (FIG. 5 PAGE 0, PAGE 1) in a predetermined file (FIG. 5 AV1) and assigning device independent locations in a logical external storage space (VF0, VF1); (b) writing the pages (PAGE 0, PAGE 1) into a cache and indexing the cache location of said pages by the logical external storage space address (VF0, VF1); (c) responsive to an update of a page (FIG. 5 PAGE 1') not common to said first (AV1) and second (AV2) files, assigning another logical external storage space (VF2 for PAGE 1') and storing the updated pages in cache in said another storage space location; and (d) responsive to an update of a page common (PAGE 0) to the first (AV1) and second (AV2) files, updating the page in place in the cache (FIG. 6 VF0'), otherwise responsive to an update of a page not in common (PAGE 1"), writing the update in cache at yet another logical external storage space (FIG. 6 VF2") and retaining the original page at its former cache location (FIG. 6 VF2').

Claim 3

The method according to claim 1, wherein said method includes the further steps as pertains to a nonvolatile cache of: (e) responsive to a full cache, allocating space on external storage, copying updated pages to that space, and forming a concordance between the logical external space location and the physical location in external storage.

Claim 4

The method according to claim 1, wherein the cache is a non-volatile cache selected from a set consisting of addressable memory formed from bistable remanant magnetic material or bistable battery back electrostatic material.

Claim 5

In a demand paging storage system of the type in which a CPU accesses each page according to its address in a linear, virtual address space from a RAM page organized cache, and further in which an accessed page not available in cache is staged from a location in an external backing store to said cache, each CPU page access to said cache including a virtual to real address translation, wherein a CPU implemented method for accessing pages in said cache without disturbing logical views of said pages and without having to assign additional backing store thereto, said logical views being expressed as a counterpart first and second page-organized file, comprises the steps of: (a) translating each CPU page access from the linear virtual page address to an address in a second linear virtual address space representing cache locations, translating the address in the second linear virtual address space into a real address in the external backing store, and writing the page into the cache at its address in the second linear virtual address space from the backing store unless the page has already been written into the cache; and (b) responsive to each access from the CPU seeking to update a page stored in cache by writing the updated page in its second linear virtual address space cache location if the page is common to the first and second page organized files, otherwise, writing the updated page to another cache location having another second linear virtual address space address.

Claim 6

In a demand paging storage system of the type in which a CPU accesses each page according to its address in a linear, virtual address space from a RAM page organized cache, and further in which an accessed page not available in cache is staged from a location in an external backing store to said cache, each CPU page access to said cache including a virtual to real address translation, wherein a CPU implemented method for accessing pages in said cache without disturbing logical views of said pages and without having to assign additional backing store thereto, said logical views being expressed as a counterpart first and second page-organized file, comprises the steps of: (a) translating each CPU page access from the linear virtual page address to an address in a second linear virtual address space representing cache locations, translating the address in the second linear virtual address space into a real address in the external backing store, and writing the page into the cache at its address in the second linear virtual address space from the backing store unless the page has already been written into the cache; and (b) responsive to each access from the CPU seeking to update a page stored in cache by writing the updated page in its second linear virtual address space cache location if the page is common to the first and second page organized files, otherwise, writing the updated page to another cache location having another second linear virtual address space address.

Claim 7

The method according to claim 4, wherein the method further includes the step of (c) writing the pages out from the cache to real addresses in the external backing store only upon update to the cache stored page.

Claim 8

The method according to claim 4, wherein the method further includes the step of (d) omitting the invalidation of the page in the cache as long as its second linear virtual address remains the unchanged.