US5084876A
Expired / Lapsed
US
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Method and apparatus for testing digital circuits
Assignee: Agilent Technologies Inc
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Filing: 1989-12-29
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Granted: 1992-01-28
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Expires: 2009-12-29
Abstract
Abstract Means are provided which aid in generating programs for testing digital modules. Formal hierarchical descriptions (e.g. in Prolog) of the module without and with a defined fault are stored in a storage device comprising two stores backed up by a submodule store. The two moldule descriptions are fed into registers. Then, repeatedly, (a) an unfolding processor works down the hierarchy, (b) a simplification processor simplifies the descriptions using a variety of logical and arithmetical rules, and (c) a discrimination condition extraction processor extracts discrimination conditions which are common to both module descriptions and necessary (i.e. must be satisfied as part of the final test programme). Another processor has discrimination condition storage means and discrimination condition consistency checking means coupled to it. The processors use common rules, stored in a logical rules store, which rely heavily on expressions of the if-then-else form. The simplification processor may allow operator intervention so that the operator may guide and/or perform certain simplifications and/or their order. Thus a sequence of discrimination conditions is found, acting to gradually focus down onto the point where the two modules--sound and faulty--differ.
Inventors
- 👤 Robert K. Welham
- 👤 Ajay Gupta
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 03:14
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318307
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
113 words
Apparatus for assisting in the generation of a test program for testing a digital circuit assembly for a predetermined fault comprising: means for storing formal hierarchical descriptions sufficient to define the assembly without and with the fault; register means for holding for the assembly without the fault and the assembly with the fault a representation of at least a part of the assembly derived from its formal description as content; unfolding processor means for hierarchically expanding the contents of the register means; simplification processor means for applying simplification rules to the contents of the register means; and discrimination condition extraction processor means for extracting discrimination conditions from the contents of the register means.
Claim 2
Dependent Claim
113 words
Apparatus for assisting in the generation of a test program for testing a digital circuit assembly for a predetermined fault comprising: means for storing formal hierarchical descriptions sufficient to define the assembly without and with the fault; register means for holding for the assembly without the fault and the assembly with the fault a representation of at least a part of the assembly derived from its formal description as content; unfolding processor means for hierarchically expanding the contents of the register means; simplification processor means for applying simplification rules to the contents of the register means; and discrimination condition extraction processor means for extracting discrimination conditions from the contents of the register means.
Claim 3
Dependent Claim
61 words
The apparatus according to claim 1 wherein said means for storing the formal hierarchical descriptions comprise primary storage means for storing the formal hierarchical descriptions relating to the assembly without the fault and the assembly with the fault, and a submodule storage means coupled thereto for storing descriptions of submodules which may be repeated in the assemblies and/or common to both.
Claim 4
Dependent Claim
50 words
The apparatus according to claim 2 wherein said primary storage means comprise first storage means for storing a complete description of one of the assemblies, and second storage means for storing a description of a manner in which the assembly with the fault differs from the assembly without the fault.
Claim 5
Dependent Claim
29 words
The apparatus according to claim 1 wherein the discrimination condition extraction processor is coupled to a discrimination condition storage means for accumulating successive discrimination conditions determined by that processor.
Claim 6
Dependent Claim
56 words
The apparatus according to claim 4 wherein the discrimination condition extraction processor and the discrimination condition storage means have coupled to them discrimination condition consistency checking means for checking the consistency of successive discrimination conditions determined by the discrimination condition extraction processor against the accumulating successive discrimination conditions stored by the discrimination condition extraction storage means.
Claim 7
Independent Claim
35 words
The apparatus according to any previous claim further comprising logical relations storage means couple to and storing rules used in common by a plurality of said processor means and the discrimination condition consistency checking means.
Claim 8
Dependent Claim
36 words
The apparatus according to claim 6 wherein the rules stored by said logical relations storage means comprise logical rules, arithmetical rules, and rules relating to specific circuit properties of each assembly without and with the fault.
Claim 9
Dependent Claim
23 words
The apparatus according to any previous claim 1 through 5 wherein said simplification processor allows an operator to intervene to perform certain simplifications.
Claim 10
Dependent Claim
46 words
The apparatus according to any previous claim 1 through 5 further comprising loading processor means for loading into said register means a plurality of items of said formal descriptions in sequence with an operator of each said processor means on the contents of the register means.
Claim 11
Dependent Claim
25 words
The apparatus according to any previous claim 1 through 5 further comprising control means for controlling a sequence of operation of each said processor means.
Claim 12
Independent Claim
81 words
A method of assisting in generation of a test program for testing a digital circuit assembly for a predetermined fault comprising: storing formal hierarchical descriptions sufficient to define the assembly without and with the fault; storing for the assembly without the fault and for the assembly with the fault a representation of at least a part of the assembly derived from its formal description; hierarchically expanding the stored representation; simplifying the stored representation; and extracting discrimination conditions from the stored representations.
Claim 13
Independent Claim
81 words
A method of assisting in generation of a test program for testing a digital circuit assembly for a predetermined fault comprising: storing formal hierarchical descriptions sufficient to define the assembly without and with the fault; storing for the assembly without the fault and for the assembly with the fault a representation of at least a part of the assembly derived from its formal description; hierarchically expanding the stored representation; simplifying the stored representation; and extracting discrimination conditions from the stored representations.
Claim 14
Dependent Claim
52 words
The method of claim 11 wherein the step of storing the formal hierarchical description comprises: storing the formal hierarchical description relating to the assembly without the fault and the assembly with the fault; and storing the respective description of submodules of the assembly without the fault and the assembly with the fault.
Claim 15
Dependent Claim
15 words
The method of claim 11 further comprising the step of storing accumulated successive discrimination conditions.
Claim 16
Dependent Claim
21 words
The method of claim 12 comprising the step of checking consistency of successive discrimination conditions against the stored accumulated discrimination conditions.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-01-27 | 1995-07-29 | 1996-01-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-01-27 | 1999-07-29 | 2000-01-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-01-27 | 2003-07-29 | 2004-01-28 | $7700.00 | Window Closed / Lapsed |