Synaptic element and array

Claim 2

An electronic circuit fabricated as a part of an integrated circuit, said integrated circuit having a portion containing active circuits, said portion covered by an opaque layer, including in combination: a plurality of adaptive amplifiers arranged as an array including a plurality of columns and at least one row, each of said adaptive amplifiers having a gain of magnitude much larger than 1 and including: an output node, a sense node, an inverting input node, said input node being a floating node forming the gate of at least one MOS transistor, a first capacitor for coupling an input to said adaptive amplifier to said floating node, said first capacitor having a first electrode connected to said input to said adaptive amplifier and a second electrode connected to said floating node, a second capacitor connected from said output node to said floating node, said second capacitor having a first electrode connected to said output node and a second electrode connected to said floating node, said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto both electrodes of said second capacitor; a voltage input line associated with each of said rows in said array, said voltage input line electrically connected to the first electrode of the first capacitor of each of said adaptive amplifiers associated with that particular row, a current output line associated with each of said columns in said array, said current output line electrically connected to the sense nodes of each of said adaptive amplifiers associated with that particular column.

Claim 3

The circuit of claim 1 further including winner take all means, connected to each of said current output lines, for providing a signal indicating which one of said current output lines is drawing the most current.

Claim 4

An electronic circuit fabricated as a part of an integrated circuit, said integrated circuit having a portion containing active circuits, said portion covered by an opaque layer, including in combination: a plurality of adaptive amplifiers arranged as an array including a plurality of columns and at least one row, each of said adaptive amplifiers having a gain of magnitude much larger than 1 and an offset voltage and including: an output node, a sense node, an inverting input node, said input node being a floating node forming the gate of at least one MOS transistor, a first capacitor for coupling an input to said adaptive amplifier to said floating node, said first capacitor having a first electrode connected to said input to said adaptive amplifier and a second electrode connected to said floating node, a second capacitor connected from said output node to said floating node, said second capacitor having a first electrode connected to said output node and a second electrode connected to said floating node, said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto both electrodes of said second capacitor, a sample/hold circuit associated with each of said adaptive amplifiers, each of said sample/hold circuits having an input, a sample input, and an output, said output connected to said first electrode of said first capacitor, a voltage input/output line associated with each of said rows in said array, each of said voltage input lines electrically connected to the input of each of said sample/hold circuits associated with that particular row, a current output line associated with each of said columns in said array, each of said current output lines electrically connected to the sense node of each of said adaptive amplifiers associated with that particular column, a sample/hold line associated with each of said rows in said array, each of said sample/hold lines electrically connected to the sample inputs of each of said sample/hold circuits associated with that particular row, a plurality of switch means, including control means, associated with each of said columns in said array, said switch means connected between the output nodes of each of said adaptive amplifiers associated with that particular column and the one of said input/output lines with which a particular adaptive amplifier in said column is associated, for selectively coupling the output nodes of said adaptive amplifiers to said input/output lines, a control line associated with each of said columns in said array, for activating said switch means to place the voltage on the output nodes of selected adaptive amplifiers onto said input/output lines.

Claim 5

An electronic circuit fabricated as a part of an integrated circuit, said integrated circuit having a portion containing active circuits, said portion covered by an opaque layer, including in combination: a plurality of adaptive amplifiers arranged as an array including a plurality of columns and at least one row, each of said adaptive amplifiers having a gain of magnitude much larger than 1 and an offset voltage and including: an output node, a sense node, an inverting input node, said input node being a floating node forming the gate of at least one MOS transistor, a first capacitor for coupling an input to said adaptive amplifier to said floating node, said first capacitor having a first electrode connected to said input to said adaptive amplifier and a second electrode connected to said floating node, a second capacitor connected from said output node to said floating node, said second capacitor having a first electrode connected to said output node and a second electrode connected to said floating node, said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto both electrodes of said second capacitor, a sample/hold circuit associated with each of said adaptive amplifiers, each of said sample/hold circuits having an input, a sample input, and an output, said output connected to said first electrode of said first capacitor, a voltage input/output line associated with each of said rows in said array, each of said voltage input lines electrically connected to the input of each of said sample/hold circuits associated with that particular row, a current output line associated with each of said columns in said array, each of said current output lines electrically connected to the sense node of each of said adaptive amplifiers associated with that particular column, a sample/hold line associated with each of said rows in said array, each of said sample/hold lines electrically connected to the sample inputs of each of said sample/hold circuits associated with that particular row, a plurality of switch means, including control means, associated with each of said columns in said array, said switch means connected between the output nodes of each of said adaptive amplifiers associated with that particular column and the one of said input/output lines with which a particular adaptive amplifier in said column is associated, for selectively coupling the output nodes of said adaptive amplifiers to said input/output lines, a control line associated with each of said columns in said array, for activating said switch means to place the voltage on the output nodes of selected adaptive amplifiers onto said input/output lines.

Claim 6

The circuit of claim 3 further including winner take all means, connected to each of said output lines, for providing a signal indicating which one of said current output lines is drawing the most current.