US5081053A
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Method for forming a transistor having cubic boron nitride layer
Assignee: Motors Liquidation Co
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Filing: 1990-10-15
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Granted: 1992-01-14
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Expires: 2010-10-15
Abstract
Abstract A method for forming a transistor which may be suitable for high temperature application is provided. A single crystal silicon substrate has an overlaying layer of epitaxially grown cubic boron nitride in crystallographic registry with the silicon substrate. The cubic boron nitride is epitaxially grown using laser ablation techniques and provides an electrically resistive and thermally conductive barrier. An active layer of epitaxial silicon is then grown from the layer of cubic boron nitride, such that the overlaying layer of epitaxial silicon is in crystallographic registry with the layer of boron nitride which is in crystallographic registry with the underlying silicon substrate. Appropriately doped source and drain regions and a gate electrode are provided to form the transistor. A clean crystallographic lattice match between the cubic boron nitride and surrounding silicon is obtained, thereby minimizing any stresses due to a mismatch in lattice constants and permitting the overlaying silicon active layer to be extremely thin.
Inventors
- 👤 Joseph P. Heremans
- 👤 Gary L. Doll
- 👤 Jeffrey A. Sell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:40
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10D30/0321; H10D30/0323; H10D30/60; H10D30/67; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6744; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W; H10W10/00; H10W10/10; H10W10/181; Y; Y10; Y10S; Y10S148/00; Y10S148/113; Y10S148/149; Y10S438/00; Y10S438/932
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
150 words
A method for forming a transistor suitable for use at high temperatures comprising the following steps: providing a substrate of silicon oriented along a single crystallographic axis; depositing onto a surface of said substrate a thin film layer of boron nitride, said thin film layer of boron nitride being crystallographically aligned with said substrate; depositing onto said thin film layer of boron nitride a thin film layer of silicon, said thin film layer of silicon being crystallographically aligned with said thin film layer of boron nitride; doping said thin film layer of silicon in at least two regions which are in a spaced relationship with each other to form a source region and a drain region which are separated by a region of undoped silicon; and depositing an electrical contact on said undoped region of said thin film layer of silicon so as to contact said source and drain regions.
Claim 2
Independent Claim
150 words
A method for forming a transistor suitable for use at high temperatures comprising the following steps: providing a substrate of silicon oriented along a single crystallographic axis; depositing onto a surface of said substrate a thin film layer of boron nitride, said thin film layer of boron nitride being crystallographically aligned with said substrate; depositing onto said thin film layer of boron nitride a thin film layer of silicon, said thin film layer of silicon being crystallographically aligned with said thin film layer of boron nitride; doping said thin film layer of silicon in at least two regions which are in a spaced relationship with each other to form a source region and a drain region which are separated by a region of undoped silicon; and depositing an electrical contact on said undoped region of said thin film layer of silicon so as to contact said source and drain regions.
Claim 3
Dependent Claim
22 words
A method for forming a transistor as recited in claim 1 wherein said silicon substrate is oriented essentially along the crystallographic plane.
Claim 4
Independent Claim
158 words
A method for forming a transistor suitable for use at high temperatures comprising the following steps: providing a substrate of silicon oriented essentially along the crystallographic axis; laser ablating onto a surface of said substrate a thin film layer of boron nitride, said thin film layer of boron nitride being crystallographically aligned with said substrate; depositing onto said thin film layer of boron nitride a thin film layer of silicon, said thin film layer of silicon being crystallographically aligned with said thin film layer of boron nitride; doping said thin film layer of silicon in at least two regions which are in a spaced relationship with each other to form a source region and a drain region which are separated by a region of undoped silicon within said thin film layer of silicon; and depositing an electrical contact on said undoped region of said thin film layer of silicon so as to contact said source and drain regions.
Claim 5
Independent Claim
158 words
A method for forming a transistor suitable for use at high temperatures comprising the following steps: providing a substrate of silicon oriented essentially along the crystallographic axis; laser ablating onto a surface of said substrate a thin film layer of boron nitride, said thin film layer of boron nitride being crystallographically aligned with said substrate; depositing onto said thin film layer of boron nitride a thin film layer of silicon, said thin film layer of silicon being crystallographically aligned with said thin film layer of boron nitride; doping said thin film layer of silicon in at least two regions which are in a spaced relationship with each other to form a source region and a drain region which are separated by a region of undoped silicon within said thin film layer of silicon; and depositing an electrical contact on said undoped region of said thin film layer of silicon so as to contact said source and drain regions.
References Cited (Backward Citations)
JPS61222111A
Cited
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