Semiconductor integrated circuit device and process for fabricating the same

Claim 2

A semiconductor integrated circuit device comprising: a first semiconductor region of first conductivity type formed in a semiconductor substrate; first and second MISFETs formed in said first semiconductor region and each having a gate insulating film, a gate, and source and drain regions of second conductivity type, the gates of said first and second MISFETs being connected directly with the drain regions of said second and first MISFETs, respectively, through contact holes formed in said gate insulating films thereby to construct a flip-flop circuit of a memory cell; and second semiconductor regions of the first conductivity type formed beneath a first portion of said drain regions to have substantially the same shapes as those of said contact holes and having a higher impurity concentration than that of said first semiconductor region.

Claim 3

A semiconductor integrated circuit device according to claim 1, wherein said first and second conductivity types are p-type and n-type, respectively, wherein the semiconductor substrate is of n-type conductivity, and wherein said first semiconductor region is a p-type well region formed in the n-type semiconductor substrate.

Claim 4

A semiconductor integrated circuit device according to claim 1, further comprising two resistor elements connected between the drain regions of said first and second MISFETs, respectively, and a power source potential for providing load elements of the flip-flop circuit of said memory cell.

Claim 5

A semiconductor integrated circuit device according to claim 1, further comprising third semiconductor regions of the first conductivity type, formed beneath the source regions and a second portion of the drain regions, other than said first portion, of said first and second MISFETs, the third semiconductor regions having a higher impurity concentration than that of said first semiconductor region and being provided in self-alignment with the gates of said first and second MISFETs.

Claim 6

A semiconductor integrated circuit device according to claim 1, further comprising: two switch MISFETs interposed between the drain regions of said first and second MISFETs, respectively, and a pair of data lines, wherein at least one of the gates of said first and second MISFETs is connected directly with the source or drain region of one of said switch MISFETs through second contact holes which are formed in gate insulating films of said switch MISFETs; and a fourth semiconductor region of the first conductivity type formed beneath the source or drain region of one of said switch MISFETs to have substantially the same shape as that of said second contact holes.

Claim 7

A semiconductor integrated circuit device comprising: a first semiconductor region of first conductivity type formed in a semiconductor substrate; first and second MISFETs formed in said first semiconductor region and each having a gate insulating film, a gate, and source and drain regions of second conductivity type, the gates of said first and second MISFETs being connected directly with the drain regions of said second and first MISFETs, respectively, through contact holes formed in said gate insulating films thereby to construct a flip-flop circuit of a memory cell; second semiconductor regions of the first conductivity type formed beneath a portion of said drain regions to have substantially similar shapes as those of said contact holes and having a higher impurity concentration than that of said first semiconductor region; and third semiconductor regions of the first conductivity type formed beneath portions of said drain regions other than the portions of the drain regions beneath which said second semiconductor regions are formed, and having a higher impurity concentration than that of said first semiconductor region, wherein said second semiconductor regions are deeper than said third semiconductor regions, and said second and third semiconductor regions are in contact with each other.

Claim 8

A semiconductor integrated circuit device comprising: a first semiconductor region of first conductivity type formed in a semiconductor substrate; first and second MISFETs formed in said first semiconductor region and each having a gate insulating film, a gate, and source and drain regions of second conductivity type, the gates of said first and second MISFETs being connected directly with the drain regions of said second and first MISFETs, respectively, through contact holes formed in said gate insulating films thereby to construct a flip-flop circuit of a memory cell; second semiconductor regions of the first conductivity type formed beneath a portion of said drain regions to have substantially similar shapes as those of said contact holes and having a higher impurity concentration than that of said first semiconductor region; and third semiconductor regions of the first conductivity type formed beneath portions of said drain regions other than the portions of the drain regions beneath which said second semiconductor regions are formed, and having a higher impurity concentration than that of said first semiconductor region, wherein said second semiconductor regions are deeper than said third semiconductor regions, and said second and third semiconductor regions are in contact with each other.

Claim 9

A semiconductor integrated circuit device according to claim 6, wherein said first and second conductivity types are p-type and n-type, respectively, wherein the semiconductor substrate is of n-type conductivity, and wherein said first semiconductor region is a p-type well region formed in the n-type semiconductor substrate.

Claim 10

A semiconductor integrated circuit device according to claim 7, further comprising two resistor elements connected between the drain regions of said first and second MISFETs, respectively, and a power source potential, for providing load elements of the flip-flop circuit of said memory cell.

Claim 11

A semiconductor integrated circuit device according to claim 8, wherein said two resistor elements are formed of polycrystalline silicon.

Claim 12

A semiconductor integrated circuit device according to claim 6, wherein the third semiconductor regions are in contact with the drain regions.

Claim 13

A semiconductor integrated circuit device according to claim 6, wherein each of the first and second MISFETs include a sub-region provided in the first semiconductor region, beneath the respective gates, in which a channel of the respective first and second MISFETs is to be formed, and wherein said third semiconductor regions do not reach said sub-region.

Claim 14

A semiconductor integrated circuit device according to claim 6, wherein the drain regions of the first and second MISFETs include ions, as a conductivity-determining impurity, that have a smaller diffusion coefficient than a diffusion coefficient of conductivity-determining impurity ions of the third semiconductor regions.

Claim 15

A semiconductor integrated circuit device according to claim 12, wherein impurity ions of the third semiconductor regions are boron ions, and the impurity ions of the drain regions of the first and second MISFETs are arsenic ions.

Claim 16

A semiconductor integrated circuit device according to claim 6, wherein the second and third semiconductor regions have substantially the same impurity concentrations.

Claim 17

A semiconductor integrated circuit device according to claim 6, wherein each of the source and drain regions of the first and second MISFETs include a relatively low impurity concentration sub-region and a relatively high impurity concentration sub-region, the relatively low impurity concentration sub-regions being closer to the respective gate, and wherein the third semiconductor regions extend beneath both the relatively low impurity concentration sub-region and the relatively high impurity concentration sub-region of the drain regions of the first and second MISFETs.

Claim 18

A semiconductor integrated circuit device according to claim 6, wherein the second semiconductor regions are respectively beneath the contact holes, and have a similar shape as a respective contact hole.

Claim 19

A semiconductor integrated circuit device comprising: a first semiconductor region of first conductivity type formed in a semiconductor substrate; first and second MISFETs formed in said first semiconductor region and each having a gate insulating film, a gate, and source and drain regions of second conductivity type, the gates of said first and second MISFETs being connected directly with the drain regions of said second and first MISFETs, respectively, at a first portion of said drain regions thereby to construct a flip-flop circuit of a memory cell; second semiconductor regions of the first conductivity type formed below said first portion of said drain regions, and having a higher impurity concentration than that of said first semiconductor region; and third semiconductor regions of the first conductivity type formed below a second portion of said drain regions other than said first portion, and having a higher impurity concentration than that of said first semiconductor region, wherein said second semiconductor regions are deeper than said third semiconductor regions, and said second and third semiconductor regions are in contact with each other.

Claim 20

A semiconductor integrated circuit device comprising: a first semiconductor region of first conductivity type formed in a semiconductor substrate; first and second MISFETs formed in said first semiconductor region and each having a gate insulating film, a gate, and source and drain regions of second conductivity type, the gates of said first and second MISFETs being connected directly with the drain regions of said second and first MISFETs, respectively, at a first portion of said drain regions thereby to construct a flip-flop circuit of a memory cell; second semiconductor regions of the first conductivity type formed below said first portion of said drain regions, and having a higher impurity concentration than that of said first semiconductor region; and third semiconductor regions of the first conductivity type formed below a second portion of said drain regions other than said first portion, and having a higher impurity concentration than that of said first semiconductor region, wherein said second semiconductor regions are deeper than said third semiconductor regions, and said second and third semiconductor regions are in contact with each other.

Claim 21

A semiconductor integrated circuit device according to claim 17, wherein said first and second conductivity types are p-type and n-type, respectively, wherein the semiconductor substrate if of n-type conductivity, and wherein said first semiconductor region is a p-type well region formed in the n-type semiconductor substrate.

Claim 22

A semiconductor integrated circuit device according to claim 18, further comprising two resistor elements connected between the drain regions of said first and second MISFETs, respectively, and a power source potential, for providing load elements of the flip-flop circuit of said memory cell.

Claim 23

A semiconductor integrated circuit device according to claim 19, wherein said two resistor elements are formed of polycrystalline silicon.

Claim 24

A semiconductor integrated circuit device according to claim 20, wherein said gates of said first and second MISFETs are connected to said drain regions of said second and first MISFETs through contact holes formed in said gate insulating films.

Claim 25

A semiconductor integrated circuit device according to claim 21, wherein the shape of said contact holes are similar to those of said second semiconductor regions.

Claim 26

A semiconductor integrated circuit device according to claim 22, wherein said second semiconductor regions are provided beneath the contact holes.

Claim 27

A semiconductor integrated circuit device according to claim 21, wherein said second semiconductor regions are provided beneath the contact holes.

Claim 28

A semiconductor integrated circuit device according to claim 1, wherein said second semiconductor regions are formed directly in contact with said drains.

Claim 29

A semiconductor integrated circuit device according to claim 17, wherein each of the first and second MISFETs include a sub-region provided in the first semiconductor region, beneath the respective gates, in which a channel of the respective first and second MISFETs is to be formed, and wherein said third semiconductor regions do not reach said sub-region.

Claim 30

A semiconductor integrated circuit device according to claim 4, wherein the first and second MISFETs include regions, beneath the respective gates, in which channels are to be formed, and wherein said third semiconductor regions do not extend beneath said regions, beneath the respective gates, in which the channels are to be formed.

Claim 31

A semiconductor integrated circuit device according to claim 27, wherein said second semiconductor regions do not extend beneath said regions, beneath the respective gates, in which the channels are to be formed.

Claim 32

A semiconductor integrated circuit device according to claim 1, wherein the drain regions of the first and second MISFETs include ions, as a conductivity-determining impurity, that have a smaller diffusion coefficient than a diffusion coefficient of conductivity-determining impurity ions of the third semiconductor regions.

Claim 33

A semiconductor integrated circuit device according to claim 4, wherein the third semiconductor regions are formed to be integral with the second semiconductor regions.

Claim 34

A semiconductor integrated circuit device according to claim 1, wherein the first and second MISFETs include regions, beneath the respective gates, in which channels are to be formed, and wherein said second semiconductor regions do not extend beneath said regions, beneath the respective gates, in which the channels are to be formed.

Claim 35

A semiconductor integrated circuit device having memory cells with a flip-flop circuit, comprising: a first semiconductor region of first conductivity type formed in a semiconductor substrate; a first insulating film having first and second holes, on said first semiconductor region; a second semiconductor region of second conductivity type at said first hole, and a third semiconductor region of second conductivity type; a first MISFET having a first gate electrode, and first source and drain regions of second conductivity type, and a second MISFET having a second gate electrode, and second source and drain regions of second conductivity type, said first gate electrode being on said first insulating film and connected to said second drain region and said second gate electrode being connected to said second semiconductor region and extending into said first hole, and wherein said first drain region is contiguous to said semiconductor region; a fourth semiconductor region of first conductivity type formed below a portion of said first drain region, and having a higher impurity concentration than that of said first semiconductor region; and a fifth semiconductor region of first conductivity type formed below said second semiconductor region, and having a higher impurity concentration than that of said first semiconductor region, said fifth semiconductor region extending deeper than said fourth semiconductor region.

Claim 36

A semiconductor integrated circuit device having memory cells with a flip-flop circuit, comprising: a first semiconductor region of first conductivity type formed in a semiconductor substrate; a first insulating film having first and second holes, on said first semiconductor region; a second semiconductor region of second conductivity type at said first hole, and a third semiconductor region of second conductivity type; a first MISFET having a first gate electrode, and first source and drain regions of second conductivity type, and a second MISFET having a second gate electrode, and second source and drain regions of second conductivity type, said first gate electrode being on said first insulating film and connected to said second drain region and said second gate electrode being connected to said second semiconductor region and extending into said first hole, and wherein said first drain region is contiguous to said semiconductor region; a fourth semiconductor region of first conductivity type formed below a portion of said first drain region, and having a higher impurity concentration than that of said first semiconductor region; and a fifth semiconductor region of first conductivity type formed below said second semiconductor region, and having a higher impurity concentration than that of said first semiconductor region, said fifth semiconductor region extending deeper than said fourth semiconductor region.

Claim 37

A semiconductor integrated circuit device according to claim 32, wherein said first and second conductivity types are p-type and n-type, respectively, wherein said semiconductor substrate is of n-type conductivity, and wherein said first semiconductor region is a p-type well region formed in the n-type semiconductor substrate.

Claim 38

A semiconductor integrated circuit device according to claim 33, further comprising two resistor elements connected to said first and second drain regions, respectively, and connected to a power source potential, for providing load elements of the flip-flop circuit of said memory cells.

Claim 39

A semiconductor integrated circuit device according to claim 32, wherein said fourth semiconductor region of the first conductivity type is formed in self-alignment with said first and second gate electrodes of said first and second MISFETs.

Claim 40

A semiconductor integrated circuit device according to claim 32, further comprising: a first switching MISFET interposed between said first drain region and one of a pair of data lines; and a second switching MISFET interposed between said second drain region and the other of said pair of data lines.

Claim 41

A semiconductor integrated circuit device according to claim 34, wherein said two resistor elements comprise polycrystalline silicon.

Claim 42

A semiconductor integrated circuit device according to claim 32, wherein as shape in plan view of said first hole is similar to that in plan view of said fifth semiconductor region.

Claim 43

A semiconductor integrated circuit device according to claim 32, wherein said fourth semiconductor region is contiguous to said fifth semiconductor region.