US5079450A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Self-latching logic gate for use in programmable logic array circuits
Assignee: Lattice Semiconductor Corp
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Filing: 1990-09-13
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Granted: 1992-01-07
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Expires: 2010-09-13
Abstract
Abstract A self-latching logic gate is disclosed which includes a first logic gate circuit for generating an output signal representative of a function of two or more input signals. The first logic gate circuit includes a first logic gate having at least two transistors, each transistor having first, second and third terminals. The first terminals of each transistor are connected to provide an output terminal for the self-latching logic gate and the first logic gate circuit. The second terminals of the transistors provide first and second data input terminals for the logic gate circuit. The third terminals of each transistor are connected to a common termination (i.e. ground). First and second complementary mode transistors are provided. Each includes first, second and third terminals, with the first terminal of the first transistor being connected to a source of electrical potential, the second terminals of the first and the second transistors being connected to each other to provide a common input terminal for the first and second transistors, the third terminal of the first transistor and the first terminal of the second transistor being connected to the output terminal of the first logic gate, and the third terminal of the second transistor being connected to ground. A second logic gate circuit is provided for including a second logic gate having first and second input terminals, the first input terminal being connected to the output terminal of the first logic gate circuit, the second input terminal providing a latch input terminal for the self-latching gate, and the output terminal of the second logic gate being connected to the common input terminal of the first and second transistors. In a specific embodiment, the present invention provides a NOR gate with a self-latching output, with minimal parts count and power consumption, which is suitable for use in a PAL system. In further more specific embodiments, the invention includes circuitry for verifying the state of the PAL array, circuitry for changing the polarity of the array output and circuitry for providing system security all with minimal parts counts and power consumption.
Inventors
- 👤 Vincent K. Z. Win
- 👤 Andrew K. Chan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 19:03
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17716; H03K3/027; H03K3/037
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
315 words
A self-latching logic gate comprising: first logic gate means for generating an output signal representative of a function of two or more input signals including a NOR gate having at least two transistors with each transistor having a first, a second and a third terminal, said first terminal of each transistor being connected to provide an output terminal of said first logic gate means and said self-latching logic gate, said second terminals of said transistors providing a first and a second data input terminal for said first logic gate means, and said third terminal of each transistor being connected to a common termination; a first and second complementary mode transistor, each transistor having a first, a second and a third terminal, said first terminal of said first complementary mode transistor being connected to a source of electrical potential, said second terminals of said first and said second complementary mode transistors being connected to each other to provide a common input terminal for said first and second complementary mode transistors, said third terminal of said first complementary mode transistor being connected to said output terminal of said NOR gate, said first terminal of said second complementary mode transistor being connected to said output terminal of said NOR gate, and said third terminal of said second complementary mode transistor being connected to said common termination; and second logic gate means for generating an output signal representative of a function of two or more input signals, said second logic gate means including a second logic gate having a first and a second input terminal, said first input terminal being connected to said output terminal of said first logic gate means, said second input terminal providing a latch input terminal for said self-latching logic gate, and the output terminal of said second logic gate being connected to the common input terminal of said first and second complementary mode transistors.
Claim 2
Dependent Claim
315 words
A self-latching logic gate comprising: first logic gate means for generating an output signal representative of a function of two or more input signals including a NOR gate having at least two transistors with each transistor having a first, a second and a third terminal, said first terminal of each transistor being connected to provide an output terminal of said first logic gate means and said self-latching logic gate, said second terminals of said transistors providing a first and a second data input terminal for said first logic gate means, and said third terminal of each transistor being connected to a common termination; a first and second complementary mode transistor, each transistor having a first, a second and a third terminal, said first terminal of said first complementary mode transistor being connected to a source of electrical potential, said second terminals of said first and said second complementary mode transistors being connected to each other to provide a common input terminal for said first and second complementary mode transistors, said third terminal of said first complementary mode transistor being connected to said output terminal of said NOR gate, said first terminal of said second complementary mode transistor being connected to said output terminal of said NOR gate, and said third terminal of said second complementary mode transistor being connected to said common termination; and second logic gate means for generating an output signal representative of a function of two or more input signals, said second logic gate means including a second logic gate having a first and a second input terminal, said first input terminal being connected to said output terminal of said first logic gate means, said second input terminal providing a latch input terminal for said self-latching logic gate, and the output terminal of said second logic gate being connected to the common input terminal of said first and second complementary mode transistors.
Claim 3
Dependent Claim
15 words
The self-latching gate of claim 1 wherein said second logic gate is a NOR gate.
Claim 4
Dependent Claim
18 words
The self-latching gate of claim 2 wherein said transistors in said first logic gate means are n-channel transistors.
Claim 5
Dependent Claim
385 words
A programmable logic array comprising: array logic means for providing a plurality of product terms on a plurality of selected lines on receipt of an input signal; latch means for providing a logic function of said product terms and for latching the result of said logic function, said latch means including a self-latching logic gate comprising: first logic gate means for generating an output signal representative of a function of two or more input signals including a first logic gate having at least two transistors with each transistor having a first, a second and a third terminal, said first terminal of each transistor being connected to provide an output terminal of said first logic gate means and said self-latching logic gate, said second terminals of said transistors providing a first and a second data input terminal for said first logic gate means, and said third terminal of each transistor being connected to a common termination; a first and a second complementary mode transistor, each transistor having a first, a second and a third terminal, said first terminal of said first complementary mode transistor being connected to a source of electrical potential, said second terminals of said first and said second complementary mode transistors being connected to each other to provide a common input terminal for said first and second complementary mode transistors, said third terminal of said first complementary mode transistor being connected to said output terminal of said first logic gate, said first terminal of said second complementary mode transistor being connected to said output terminal of said first logic gate, and said third terminal of said second complementary mode transistor being connected to said common termination; second logic gate means for generating an output signal representative of a function of two or more input signals, said second logic gate means including a second logic gate having a first and a second input terminal, said first input terminal being connected to said output terminal of said first logic gate means, said second input terminal providing a latch input terminal for said self-latching logic gate, and the output terminal of said second logic gate being connected to the common input terminal of said first and second complementary mode transistors; and verification circuit means for use with said programmable logic array for verifying the state thereof.
Claim 6
Dependent Claim
385 words
A programmable logic array comprising: array logic means for providing a plurality of product terms on a plurality of selected lines on receipt of an input signal; latch means for providing a logic function of said product terms and for latching the result of said logic function, said latch means including a self-latching logic gate comprising: first logic gate means for generating an output signal representative of a function of two or more input signals including a first logic gate having at least two transistors with each transistor having a first, a second and a third terminal, said first terminal of each transistor being connected to provide an output terminal of said first logic gate means and said self-latching logic gate, said second terminals of said transistors providing a first and a second data input terminal for said first logic gate means, and said third terminal of each transistor being connected to a common termination; a first and a second complementary mode transistor, each transistor having a first, a second and a third terminal, said first terminal of said first complementary mode transistor being connected to a source of electrical potential, said second terminals of said first and said second complementary mode transistors being connected to each other to provide a common input terminal for said first and second complementary mode transistors, said third terminal of said first complementary mode transistor being connected to said output terminal of said first logic gate, said first terminal of said second complementary mode transistor being connected to said output terminal of said first logic gate, and said third terminal of said second complementary mode transistor being connected to said common termination; second logic gate means for generating an output signal representative of a function of two or more input signals, said second logic gate means including a second logic gate having a first and a second input terminal, said first input terminal being connected to said output terminal of said first logic gate means, said second input terminal providing a latch input terminal for said self-latching logic gate, and the output terminal of said second logic gate being connected to the common input terminal of said first and second complementary mode transistors; and verification circuit means for use with said programmable logic array for verifying the state thereof.
Claim 7
Dependent Claim
353 words
The programmable logic array of claim 4 wherein said verification circuit comprises: third logic gate means for generating an output signal representative of a function of two or more input signals, said input signals being provided by the product terms on said selected lines, said third logic gate means including a third logic gate having at least two transistors with each transistor having a first, a second and a third terminal, said first terminal of each transistor being connected to provide an output terminal of said third logic gate means, said second terminals of said transistors providing a first and a second data input terminal for said third logic gate means, and said third terminal of each transistor being connected to a common termination; a third and a fourth complementary mode transistor, each transistor having a first, a second and a third terminal, said first terminal of said third complementary mode transistor being connected to a source of electrical potential, said second terminals of said third and said fourth complementary mode transistors being connected to each other to provide a common input terminal for said third and fourth complementary mode transistors, said third terminal of said third complementary mode transistor being connected to said output terminal of said third logic gate, said first terminal of said fourth complementary mode transistor being connected to said output terminal of said third logic gate, and said third terminal of said fourth complementary mode transistor being connected to said common termination; and fourth logic gate means for generating an output signal representative of a function of two or more input signals, and fourth logic gate means including a fourth logic gate having a first and a second input terminal, said first input terminal being connected to said output terminal of said third logic gate means, said second input terminal being connected to the common input terminal of said third and fourth complementary mode transistors and an output terminal of a fifth logic gate, said fourth logic gate means further including means for connecting said output terminal of said first logic gate means of said self-latching logic gate.
Claim 8
Dependent Claim
16 words
The programmable logic array of claim 5 including security circuit means for inhibiting said verification circuit.
Claim 9
Dependent Claim
63 words
The programmable logic array of claim 6 wherein said security circuit means includes a transistor having a first, second and a third terminals, said first terminal being connected to the output of said third logic gate of said verification circuit, said second terminal being connected to an output of said array logic means, and said third terminal being connected to said common termination.
Claim 10
Dependent Claim
388 words
A programmable logic array comprising: array logic means for providing a plurality of product terms on a plurality of selected lines on receipt of an input signal; latch means for providing a logic function of said product terms and for latching the result of said logic function, said latch means including a self-latching logic gate comprising: first logic gate means for generating an output signal representative of a function of two or more input signals including a first logic gate having at least two transistors with each transistor having a first, a second and a third terminal, said first terminal of each transistor being connected to provide an output terminal of said first logic gate means and said self-latching logic gate, said second terminals of said transistors providing a first and a second data input terminal for said first logic gate means, and said third terminal of each transistor being connected to a common termination; a first and a second complementary mode transistor; each transistor having a first, a second and a third terminal, said first terminal of said first complementary mode transistor being connected to a source of electrical potential, said second terminals of said first and said second complementary mode transistors being connected to each other to provide a common input terminal for said first and second complementary mode transistors, said third terminal of said first complementary mode transistor being connected to said output terminal of said first logic gate, said first terminal of said second complementary mode transistor being connected to said output terminal of said first logic gate, and said third terminal of said second complementary mode transistor being connected to said common termination; second logic gate means for generating an output signal representative of a function of two or more input signals, said second logic gate means including a second logic gate having a first and a second input terminal, said first input terminal being connected to said output terminal of said first logic gate means, said second input terminal providing a latch input terminal for said self-latching logic gate, and the output terminal of said second logic gate being connected to the common input terminal of said first and second complementary mode transistors; and polarity circuit means for signaling a change in the polarity of the signals output from said latch means.
Claim 11
Dependent Claim
388 words
A programmable logic array comprising: array logic means for providing a plurality of product terms on a plurality of selected lines on receipt of an input signal; latch means for providing a logic function of said product terms and for latching the result of said logic function, said latch means including a self-latching logic gate comprising: first logic gate means for generating an output signal representative of a function of two or more input signals including a first logic gate having at least two transistors with each transistor having a first, a second and a third terminal, said first terminal of each transistor being connected to provide an output terminal of said first logic gate means and said self-latching logic gate, said second terminals of said transistors providing a first and a second data input terminal for said first logic gate means, and said third terminal of each transistor being connected to a common termination; a first and a second complementary mode transistor; each transistor having a first, a second and a third terminal, said first terminal of said first complementary mode transistor being connected to a source of electrical potential, said second terminals of said first and said second complementary mode transistors being connected to each other to provide a common input terminal for said first and second complementary mode transistors, said third terminal of said first complementary mode transistor being connected to said output terminal of said first logic gate, said first terminal of said second complementary mode transistor being connected to said output terminal of said first logic gate, and said third terminal of said second complementary mode transistor being connected to said common termination; second logic gate means for generating an output signal representative of a function of two or more input signals, said second logic gate means including a second logic gate having a first and a second input terminal, said first input terminal being connected to said output terminal of said first logic gate means, said second input terminal providing a latch input terminal for said self-latching logic gate, and the output terminal of said second logic gate being connected to the common input terminal of said first and second complementary mode transistors; and polarity circuit means for signaling a change in the polarity of the signals output from said latch means.
Claim 12
Dependent Claim
125 words
The programmable logic array of claim 8 wherein said polarity circuit means includes a transistor and a NOR gate, said transistor including a first, a second and a third terminal, said first terminal being connected to a source of electrical potential, said second terminal being an input terminal thereof and being connected to an output of said NOR gate and said third terminal being connected to a first input of said NOR gate, a second input of said NOR gate being connected to a first output of said array logic means and said first input of said NOR gate being connected to a second output of said array logic means, the output of said polarity circuit being provided by the third terminal of said transistor.
Claim 13
Dependent Claim
315 words
A self-latching gate comprising: first logic gate means for generating an output signal representative of a function of two or more input signals including a first logic gate having at least two transistors with each transistor having a first, a second and a third terminal, said first terminal of each transistor being connected to provide an output terminal of said first logic gate means and said self-latching logic gate, said second terminals of said transistors providing a first and a second data input terminal for said first logic gate means, and said third terminal of each transistor being connected to a common termination; a first and second complementary mode transistor, each transistor having a first, a second and a third terminal, said first terminal of said first complementary mode transistor being connected to a source of electrical potential, said second terminals of said first and said second complementary mode transistors being connected to each other to provide a common input terminal for said first and second complementary mode transistors, said third terminal of said first complementary mode transistor being connected to said output terminal of said first logic gate, said first terminal of said second complementary mode transistor being connected to said output terminal of said first logic gate, and said third terminal of said second complementary mode transistor being connected to said common termination; and second logic gate means for generating an output signal representative of a function of two or more input signals, said second logic gate means being a NOR gate having a first and a second input terminal, said first input terminal being connected to said output terminal of said first logic gate means, said second input terminal providing a latch input terminal for said self-latching logic gate, and the output terminal of said NOR gate being connected to the common input terminal of said first and second complementary mode transistors.
Claim 14
Dependent Claim
315 words
A self-latching gate comprising: first logic gate means for generating an output signal representative of a function of two or more input signals including a first logic gate having at least two transistors with each transistor having a first, a second and a third terminal, said first terminal of each transistor being connected to provide an output terminal of said first logic gate means and said self-latching logic gate, said second terminals of said transistors providing a first and a second data input terminal for said first logic gate means, and said third terminal of each transistor being connected to a common termination; a first and second complementary mode transistor, each transistor having a first, a second and a third terminal, said first terminal of said first complementary mode transistor being connected to a source of electrical potential, said second terminals of said first and said second complementary mode transistors being connected to each other to provide a common input terminal for said first and second complementary mode transistors, said third terminal of said first complementary mode transistor being connected to said output terminal of said first logic gate, said first terminal of said second complementary mode transistor being connected to said output terminal of said first logic gate, and said third terminal of said second complementary mode transistor being connected to said common termination; and second logic gate means for generating an output signal representative of a function of two or more input signals, said second logic gate means being a NOR gate having a first and a second input terminal, said first input terminal being connected to said output terminal of said first logic gate means, said second input terminal providing a latch input terminal for said self-latching logic gate, and the output terminal of said NOR gate being connected to the common input terminal of said first and second complementary mode transistors.
Claim 15
Dependent Claim
205 words
A self-latching logic gate comprising: first and second complementary mode transistors, each transistor having a first, a second and a third terminal, said first terminal of said first complementary mode transistor being connected to a source of electrical potential, said second terminals of said first and said second complementary mode transistors being connected to each other to provide a common input terminal for said first and second complementary mode transistors, said third terminal of said first complementary mode transistor being the input terminal of said self-latching logic gate and being connected to the first terminal of said second complementary mode transistor, said third terminal of said second complementary mode transistor being connected to ground and logic gate means for generating an output signal representative of a function of two or more input signals, said logic gate means being a NOR gate having a first and a second input terminal, said first input terminal being connected to said input terminal of said self-latching logic gate, said second input terminal of said NOR gate providing a latch input terminal for said self-latching logic gate, and an output terminal of said NOR gate being connected to the common input terminal of said first and second complementary mode transistors.
Claim 16
Dependent Claim
205 words
A self-latching logic gate comprising: first and second complementary mode transistors, each transistor having a first, a second and a third terminal, said first terminal of said first complementary mode transistor being connected to a source of electrical potential, said second terminals of said first and said second complementary mode transistors being connected to each other to provide a common input terminal for said first and second complementary mode transistors, said third terminal of said first complementary mode transistor being the input terminal of said self-latching logic gate and being connected to the first terminal of said second complementary mode transistor, said third terminal of said second complementary mode transistor being connected to ground and logic gate means for generating an output signal representative of a function of two or more input signals, said logic gate means being a NOR gate having a first and a second input terminal, said first input terminal being connected to said input terminal of said self-latching logic gate, said second input terminal of said NOR gate providing a latch input terminal for said self-latching logic gate, and an output terminal of said NOR gate being connected to the common input terminal of said first and second complementary mode transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-01-06 | 1995-07-08 | 1996-01-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-01-06 | 1999-07-08 | 2000-01-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-01-06 | 2003-07-08 | 2004-01-07 | $7700.00 | Window Closed / Lapsed |