US5072448A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Quasi-random digital sequence detector
Assignee: Motorola Solutions Inc
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Filing: 1989-11-02
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Granted: 1991-12-10
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Expires: 2009-11-02
Abstract
Abstract Errors in a predetermined digital sequence are detected by utilizing a detector which includes memory elements such as a series shift register, and logic gates for detecting a predetermined subsequence. Errors are detected by comparing each bit in the data stream with the output of the memory. Logic gates inhibit the detection of an error in response to the subsequence detection.
Inventors
- 👤 Keith E. Atwell
- 👤 Harold A. Vaghy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 12:26
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/004; H04L1/0045; H04L1/0056; H04L1/0061
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
113 words
A detector for detecting errors in a predetermined sequence of bits in a digital data stream comprising: a) memory means for receiving and storing a plurality of bits in said data stream, said memory means having a plurality of memory elements and an output whose digital state depends on the contents of said elements; b) logic means for detecting a predetermined subsequence in said sequence based on the contents of said elements; c) means for detecting errors in said predetermined sequence by comparing each bit in said data stream with the state of said output; and d) means for inhibiting said error detecting means in response to said logic means detecting said subsequence.
Claim 2
Dependent Claim
113 words
A detector for detecting errors in a predetermined sequence of bits in a digital data stream comprising: a) memory means for receiving and storing a plurality of bits in said data stream, said memory means having a plurality of memory elements and an output whose digital state depends on the contents of said elements; b) logic means for detecting a predetermined subsequence in said sequence based on the contents of said elements; c) means for detecting errors in said predetermined sequence by comparing each bit in said data stream with the state of said output; and d) means for inhibiting said error detecting means in response to said logic means detecting said subsequence.
Claim 3
Dependent Claim
14 words
The detector according to claim 1 wherein said memory means comprises a shift register.
Claim 4
Dependent Claim
20 words
The detector according to claim 2 wherein said logic means comprises logic gates connected to stages of said shift register.
Claim 5
Dependent Claim
23 words
The detector according to claim 1 wherein said inhibiting means comprises at least one logic gate coupled to inhibit said error detecting means.
Claim 6
Dependent Claim
37 words
The detector according to claim 1 wherein said inhibiting means comprises means connected to said memory means for changing the state of a received bit before said memory means receives same upon the detection of said subsequence.
Claim 7
Dependent Claim
14 words
The detector according to claim 1 wherein said sequence is a quasi-random data sequence.
Claim 8
Dependent Claim
16 words
The detector according to claim 6 wherein said sequence comprises a quasi-random signal source (QRSS) sequence.
Claim 9
Dependent Claim
27 words
The detector according to claim 1 in which the number of said memory elements does not exceed the amount of memory utilized to generate said predetermined sequence.
Claim 10
Dependent Claim
16 words
The detector according to claim 1 wherein said memory means consecutively receives and stores said bits.
Claim 11
Independent Claim
105 words
A method of detecting errors in a predetermined sequence of bits in a digital data stream comprising the steps of: a) receiving and storing a plurality of bits in said data stream in a plurality of memory elements; b) generating an output whose digital state depends on the contents of said memory elements; c) detecting a predetermined subsequence in said sequence based on the contents of said memory elements; d) detecting errors in said predetermined sequence by comparing each bit in the data stream with the state of said output; and e) inhibiting the detecting of errors in response to the detection of said subsequence.
Claim 12
Independent Claim
105 words
A method of detecting errors in a predetermined sequence of bits in a digital data stream comprising the steps of: a) receiving and storing a plurality of bits in said data stream in a plurality of memory elements; b) generating an output whose digital state depends on the contents of said memory elements; c) detecting a predetermined subsequence in said sequence based on the contents of said memory elements; d) detecting errors in said predetermined sequence by comparing each bit in the data stream with the state of said output; and e) inhibiting the detecting of errors in response to the detection of said subsequence.
Claim 13
Dependent Claim
34 words
The method according to claim 10 wherein said sequence comprises a quasi-random sequence and wherein the number of said memory elements does not exceed the amount of memory utilized in generating said quasi-random sequence.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-12-09 | 1995-06-10 | 1995-12-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-12-09 | 1999-06-10 | 1999-12-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-12-09 | 2003-06-10 | 2003-12-10 | $7700.00 | Window Closed / Lapsed |