US5070447A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Interrupt circuit and interrupt processing method for microcomputer
Assignee: Sanyo Electric Co Ltd
•
Filing: 1989-12-28
•
Granted: 1991-12-03
•
Expires: 2009-12-28
Abstract
Abstract An interrupt circuit for a microcomputer, in which requests for multiple interrupt processing arise at the same time, are executed in the assigned priority order. To assign a processing priority, the interrupt circuit comprises a first priority assignment control circuit and a second priority assignment control circuit. Furthermore, in order to execute a high priority interrupt processing with a minimum lag time, the present invention comprises the steps of: issuing a software interrupt request signal assigned a lower priority while executing an interrupt request based on a request signal assigned a high priority level; executing a minimum required processing based on the request signal with a high priority level; executing and completing processing based on a request signal assign a low priority level; and resuming, by the software interrupt request signal, a rest part of the interrupted processing based on the request signal with a high priority level, whereby the plurality of interrupt requests which occurred at the same time can be processed with high efficiency
Inventors
- 👤 Hiroshi Koyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 11:01
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F9/4818; G06F9/4831
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
216 words
An interrupt circuit for a microcomputer, comprising: (a) an interrupt control circuit having a first input terminal to which a first interrupt request signal assigned to high priority level is applied, and a second input terminal to which a second interrupt request signal assigned to a low priority level is applied, said interrupt control circuit being capable of performing an interrupt processing based on each interrupt request signal; (b) a first priority assignment control circuit for producing said first and second interrupt request signals to said first and second input terminals, which is capable of assigning one of said high priority level and said low priority level to each of a plurality of interrupt request signals; and (c) a second priority assignment control circuit for producing a software interrupt request signal to said second input terminal, which is capable of assigning a low priority level to said software interrupt request signal different from said plurality of interrupt request signals, said software interrupt request signal being produced while a minimum required interrupt processing based on said first interrupt request signal is being carried out so that an interrupt processing based on said second interrupt request signal is carried out before said software interrupt request signal enables a remaining interrupt processing based on said first interrupt request signal.
Claim 2
Dependent Claim
216 words
An interrupt circuit for a microcomputer, comprising: (a) an interrupt control circuit having a first input terminal to which a first interrupt request signal assigned to high priority level is applied, and a second input terminal to which a second interrupt request signal assigned to a low priority level is applied, said interrupt control circuit being capable of performing an interrupt processing based on each interrupt request signal; (b) a first priority assignment control circuit for producing said first and second interrupt request signals to said first and second input terminals, which is capable of assigning one of said high priority level and said low priority level to each of a plurality of interrupt request signals; and (c) a second priority assignment control circuit for producing a software interrupt request signal to said second input terminal, which is capable of assigning a low priority level to said software interrupt request signal different from said plurality of interrupt request signals, said software interrupt request signal being produced while a minimum required interrupt processing based on said first interrupt request signal is being carried out so that an interrupt processing based on said second interrupt request signal is carried out before said software interrupt request signal enables a remaining interrupt processing based on said first interrupt request signal.
Claim 3
Dependent Claim
80 words
An interrupt circuit according to claim 1, wherein said first priority assignment control circuit comprises: (a) a plurality of first latch circuits for assigning one of said high priority level and said low priority level to each of said plurality of interrupt request signals; and (b) a plurality of priority assignment selectors for applying each of said plurality of interrupt request signals to one of said first and second input terminals based on an output from said first latch circuits.
Claim 4
Dependent Claim
102 words
An interrupt circuit according to claim 2, wherein said second priority assignment control circuit comprises: (a) a second latch circuit for latching said software interrupt request signal; (b) a third latch circuit for latching a software priority setting data for assigning said low priority level to said software interrupt request signal; and (c) a changeover circuit for assigning said low priority level to said software interrupt request signal based on the software priority setting data, whereby said software interrupt request signal is applied to said second input terminal of said interrupt control circuit through said changeover circuit and said priority assignment selectors.
Claim 5
Dependent Claim
130 words
An interrupt processing method for use in microprocessors for executing interrupt processing in response to either a first interrupt request signal assigned to a high priority level or a second interrupt request signal assigned to a low priority level, the method comprising the steps of: assigning a low priority to a software interrupt request signal according to a predetermined instruction included in a program of said microcomputer; issuing said software interrupt request signal and executing a minimum required processing of said first interrupt request signal during processing of said first interrupt request signal; executing processing of said second interrupt request signal; terminating processing of said second interrupt request signal; and resuming a rest of the processing of said interrupted first request signal in response to said software interrupt request signal.
Claim 6
Dependent Claim
130 words
An interrupt processing method for use in microprocessors for executing interrupt processing in response to either a first interrupt request signal assigned to a high priority level or a second interrupt request signal assigned to a low priority level, the method comprising the steps of: assigning a low priority to a software interrupt request signal according to a predetermined instruction included in a program of said microcomputer; issuing said software interrupt request signal and executing a minimum required processing of said first interrupt request signal during processing of said first interrupt request signal; executing processing of said second interrupt request signal; terminating processing of said second interrupt request signal; and resuming a rest of the processing of said interrupted first request signal in response to said software interrupt request signal.
References Cited (Backward Citations)
GB1233601A
Cited
US3641505A
Cited
US3949371A
Cited
US4250546A
Cited
US4495571A
Cited
US4319338A
Cited
US4488227A
Cited
US4636944A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-12-02 | 1995-06-03 | 1995-12-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-12-02 | 1999-06-03 | 1999-12-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-12-02 | 2003-06-03 | 2003-12-03 | $7700.00 | Window Closed / Lapsed |