US5070386A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Passivation layer structure with through-holes for semiconductor device
Assignee: Seiko Instruments Inc
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Filing: 1990-07-30
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Granted: 1991-12-03
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Expires: 2010-07-30
Abstract
Abstract A passivation layer covering a metal wire and semiconductor surface of a semiconductor integrated circuit composed of a metal-oxide-semiconductor (MOS) type transistor is a double-layer comprising a silicon nitride (P-SiN) layer formed by plasma CVD method and a phosphorus silicide glass (PSG) layer beneath the silicon nitride layer, and the P-SiN layer has a vacant region (a window) at the portion more than 20 μm and less than 100 μm away from an edge of a gate oxide layer of the transistor.
Inventors
- 👤 Yukihiro Imura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 14:06
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/40; H10W74/43; H10W74/10; H10W74/131; H10W74/147
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
82 words
A semiconductor device comprising: a semiconductor substrate; a MOS transistor provided on said semiconductor substrate; and a double passivation layer covering said MOS transistor and said semiconductor substrate and comprising a phosphorus silicon nitride layer and a phosphorus silicate glass layer beneath said silicon nitride layer, said double passivation layer having a window only in said phosphorus silicon nitride layer and not in said phosphoros silicate glass layer, said window being effective to permit the escape of contaminants from the semiconductor device.
Claim 2
Dependent Claim
82 words
A semiconductor device comprising: a semiconductor substrate; a MOS transistor provided on said semiconductor substrate; and a double passivation layer covering said MOS transistor and said semiconductor substrate and comprising a phosphorus silicon nitride layer and a phosphorus silicate glass layer beneath said silicon nitride layer, said double passivation layer having a window only in said phosphorus silicon nitride layer and not in said phosphoros silicate glass layer, said window being effective to permit the escape of contaminants from the semiconductor device.
Claim 3
Dependent Claim
34 words
A semiconductor device as claimed in claim 1, wherein said window is provided at a portion between 20 μm and 100 μm away from an edge of a gate electrode of said MOS transistor.
Claim 4
Dependent Claim
46 words
A passivation layer for a MOS transistor comprising: a silicate glass layer and a silicon nitride layer on the silicate layer, wherein said silicon nitride layer has at least one through-hole passing only through said silicon nitrite layer in a region adjacent to the MOS transistor.
Claim 5
Dependent Claim
46 words
A passivation layer for a MOS transistor comprising: a silicate glass layer and a silicon nitride layer on the silicate layer, wherein said silicon nitride layer has at least one through-hole passing only through said silicon nitrite layer in a region adjacent to the MOS transistor.
Claim 6
Dependent Claim
34 words
A passivation layer for a MOS transistor as in claim 3, wherein each said through-hole is between 20 μm and 100 μm away from an edge of a gate electrode of the MOS transistor.
Claim 7
Dependent Claim
64 words
A passivation layer for a semiconductor device having electrodes comprising: a first layer comprising of phosphorus silicate glass substantially covering the semiconductor device, a second layer comprising of phosphorus silicon nitride substantially covering said first layer, and means defining at least one through-hole only through said second layer and not through said first layer for permitting the escape of contaminants from the semiconductor device.
Claim 8
Dependent Claim
64 words
A passivation layer for a semiconductor device having electrodes comprising: a first layer comprising of phosphorus silicate glass substantially covering the semiconductor device, a second layer comprising of phosphorus silicon nitride substantially covering said first layer, and means defining at least one through-hole only through said second layer and not through said first layer for permitting the escape of contaminants from the semiconductor device.
Claim 9
Dependent Claim
33 words
A passivation layer for a semiconductor device as in claim 5, wherein each said through-hole is between 20 μm and 100 μm away from an edge of an electrode of the semiconductor device.
Claim 10
Dependent Claim
31 words
A passivation layer for a semiconductor device as in claim 5, wherein each said through-hole is more than 20 μm away from any edge of any electrode of the semiconductor device.
Claim 11
Dependent Claim
41 words
A passivation layer for a semiconductor device as in claim 7; wherein the semiconductor device includes a plurality of transistors, and at least one through-hole is less than 100 μm away from an electrode of at least one of the transistors.
Claim 12
Dependent Claim
36 words
A passivation layer for a semiconductor device as in claim 7; wherein each said through-hole is associated with a corresponding electrode of the semiconductor device and is less than 100 μm away from the corresponding electrode.
References Cited (Backward Citations)
US4406053A
Cited
JPS57208162A
Cited
JPS59100559A
Cited
JPS59110122A
Cited
JPS59219933A
Cited
US4870470A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-12-02 | 1995-06-03 | 1995-12-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-12-02 | 1999-06-03 | 1999-12-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-12-02 | 2003-06-03 | 2003-12-03 | $7700.00 | Window Closed / Lapsed |