US5070304A
Expired / Lapsed
US
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Distributed combiner power amplifier and method
Assignee: United States Department of the Air Force
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Filing: 1990-06-21
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Granted: 1991-12-03
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Expires: 2010-06-21
Abstract
Abstract An improved distributed amplifier usable, for example, in the gigahertz frequency range for radar and electronic warfare applications is disclosed. In the amplifier stage a combination of optimum amplifier stage loading, a reflection cancelling output network, and an amplifier capacitance hiding input arrangement are employed. The disclosure includes specific component values for one embodiment of the invention.
Inventors
- 👤 Mike L. Salib
- 👤 Marvin Cohn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 05:40
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/60; H03F3/602; H03F3/604; H03F3/605; H03F3/607
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
175 words
Distributed radio frequency power amplifier apparatus comprising the combination of: a signal delay line connected to a source of power amplifier input signals, said delay line including an n plurality of delayed signal taps spaced therealong; an n plurality of signal amplifier circuits each including an output terminal and an input terminal that is connected with one of said delay line delayed signal taps; an n plurality of impedance matching networks each having an output terminal and an input terminal that is connected with one of said signal amplifier circuit output terminals; an n-1 plurality of delay equalization delay lines each having an output terminal and an input terminal that is connected to one of said impedance matching network output terminals; and a signal power combining network having an output terminal and an n plurality of input terminals with n-1 of said input terminals being connected with one of said delay equalization delay line output terminals and the nth of said input terminals being connected directly with the unconnected nth impedance matching network output terminal.
Claim 2
Dependent Claim
175 words
Distributed radio frequency power amplifier apparatus comprising the combination of: a signal delay line connected to a source of power amplifier input signals, said delay line including an n plurality of delayed signal taps spaced therealong; an n plurality of signal amplifier circuits each including an output terminal and an input terminal that is connected with one of said delay line delayed signal taps; an n plurality of impedance matching networks each having an output terminal and an input terminal that is connected with one of said signal amplifier circuit output terminals; an n-1 plurality of delay equalization delay lines each having an output terminal and an input terminal that is connected to one of said impedance matching network output terminals; and a signal power combining network having an output terminal and an n plurality of input terminals with n-1 of said input terminals being connected with one of said delay equalization delay line output terminals and the nth of said input terminals being connected directly with the unconnected nth impedance matching network output terminal.
Claim 3
Dependent Claim
37 words
The power amplifier apparatus of claim 1 wherein each of said n signal amplifier circuits includes a plurality of active amplifier devices and an interstage impedance matching coupling network connected between two of said active amplifier devices.
Claim 4
Dependent Claim
56 words
The power amplifier apparatus of claim 2 wherein each of said n signal amplifier circuits includes two transistors connected into a cascode amplifier circuit and wherein said interstage impedance matching coupling network is connected between the output terminal of a first one of said transistors and the input terminal of the second one of said transistors.
Claim 5
Dependent Claim
16 words
The power amplifier apparatus of claim 3 wherein said transistors are gallium arsenide field effect transistors.
Claim 6
Dependent Claim
49 words
The power amplifier apparatus of claim 3 wherein each one of said n plurality of impedance matching networks includes Tee network means for coupling a high impedance output signal port of a cascode connected amplifier circuit with a lower impedance level input terminal, of said signal power combining network.
Claim 7
Dependent Claim
36 words
The power amplifier apparatus of claim 5 wherein each of said n plurality of impedance matching networks include series inductive input and output arm and shunt capacitive member means for maximizing the cascode amplifier output power.
Claim 8
Dependent Claim
14 words
The power amplifier apparatus of claim 4 wherein said n plurality consists of four.
Claim 9
Dependent Claim
115 words
Distributed power amplifier apparatus comprising the combination of: means for generating an n plurality of time displaced signal samples of the power amplifier input signal; n plural amplifier means for increasing the magnitude of each said n time displaced signal samples; delay equalizing means including n plural delay elements of unequal delay path length connected one with the output of each said n plural solid state amplifier means for equalizing the phase relationship among the amplifier output signals and for dissimilar path length cancellation of signal reflections from said n plural amplifier means; and real-time network means for combining the delay equalized output signals of said n plural amplifier means into a unitary output signal.
Claim 10
Dependent Claim
115 words
Distributed power amplifier apparatus comprising the combination of: means for generating an n plurality of time displaced signal samples of the power amplifier input signal; n plural amplifier means for increasing the magnitude of each said n time displaced signal samples; delay equalizing means including n plural delay elements of unequal delay path length connected one with the output of each said n plural solid state amplifier means for equalizing the phase relationship among the amplifier output signals and for dissimilar path length cancellation of signal reflections from said n plural amplifier means; and real-time network means for combining the delay equalized output signals of said n plural amplifier means into a unitary output signal.
Claim 11
Dependent Claim
29 words
The power amplifier apparatus of claim 8 wherein said network means includes n input nodes, one output node and n symmetrically disposed signal paths between input and output nodes.
Claim 12
Dependent Claim
32 words
The power amplifier apparatus of claim 9 wherein said n plurality is four in number and wherein said network means includes three three-terminal passive element signal combining arrays disposed in two-layered tandem.
Claim 13
Dependent Claim
24 words
The power amplifier apparatus of claim 10 wherein said passive element signal combining arrays each include a resistive element and a predetermined reactive element.
Claim 14
Dependent Claim
23 words
The power amplifier apparatus of claim 8 wherein said means for generating an n plurality of signal samples includes a tapped delay line.
Claim 15
Dependent Claim
30 words
The power amplifier of claim 8 wherein said amplifier means each include a plurality of active amplifying devices and means for optimizing the load applied to each said amplifying device.
Claim 16
Dependent Claim
20 words
The power amplifier of claim 8 wherein said delay equalizing means delay elements comprise delay lines of predetermined delay duration.
Claim 17
Dependent Claim
44 words
The power amplifier of claim 13 wherein said means for optimizing the load applied to each said amplifying device includes Tee connected inductive and capacitive network means for coupling a high output impedance amplifier circuit with a predetermined low input impedance signal combining network.
Claim 18
Dependent Claim
53 words
The power amplifier of claim 8 wherein said means for generating an n plurality of time displaced signal samples includes a tapped delay and filter network and wherein said n plural amplifier means includes n plural amplifier circuits each having an input reactance comprising a portion of said tapped delay and filter network.
Claim 19
Independent Claim
107 words
The method of operating a distributed radio frequency power amplifier comprising the steps of: generating an n plurality of clone signals each of successively increased number of increments of time delayed from the time of an input signal to said power amplifier and each substantially similar in information content to said power amplifier input signal; amplifying each of said clone signals; adjusting phase relationships between amplified clone signals to a uniphase condition said adjusting including communicating each said amplified clone signal along a path of different length and differing reflection signal cancellation phasing; combining the amplified and in phase clone signals into a unitary output power signal.
Claim 20
Independent Claim
107 words
The method of operating a distributed radio frequency power amplifier comprising the steps of: generating an n plurality of clone signals each of successively increased number of increments of time delayed from the time of an input signal to said power amplifier and each substantially similar in information content to said power amplifier input signal; amplifying each of said clone signals; adjusting phase relationships between amplified clone signals to a uniphase condition said adjusting including communicating each said amplified clone signal along a path of different length and differing reflection signal cancellation phasing; combining the amplified and in phase clone signals into a unitary output power signal.
Claim 21
Dependent Claim
19 words
The method of claim 17 wherein said amplifying step includes differing amplification degrees for successive of said clone signals.
Claim 22
Independent Claim
173 words
The method of operating an n amplifier distributed power amplifier to achieve desirable efficiency and low output voltage standing wave ratio comprising the steps of: combining the output signals of said n amplifiers into a single output signal in a bilateral real-time power combining network; delaying each of the n input signals of the power combining network along a communicating path of predetermined differing delaying time duration and differing reflected signal cancellation phasing, said delaying step thereby generating n differently delayed combining network input signals; and retarding each of the n amplifier input signals with respect to the input signal of the distributed power amplifier by a differing time interval, a time interval complementing the respective of said n predetermined differing delaying time durations, said complemented delays thereby generating n phase synchronized combining network input signals; whereby large output voltage standing wave ratio contributing reflection signals communicated via said bilateral combining network, and reflected from the n amplifiers are cancelled by phase oppositions developed in said paths of predetermined differing delaying time duration.
Claim 23
Independent Claim
173 words
The method of operating an n amplifier distributed power amplifier to achieve desirable efficiency and low output voltage standing wave ratio comprising the steps of: combining the output signals of said n amplifiers into a single output signal in a bilateral real-time power combining network; delaying each of the n input signals of the power combining network along a communicating path of predetermined differing delaying time duration and differing reflected signal cancellation phasing, said delaying step thereby generating n differently delayed combining network input signals; and retarding each of the n amplifier input signals with respect to the input signal of the distributed power amplifier by a differing time interval, a time interval complementing the respective of said n predetermined differing delaying time durations, said complemented delays thereby generating n phase synchronized combining network input signals; whereby large output voltage standing wave ratio contributing reflection signals communicated via said bilateral combining network, and reflected from the n amplifiers are cancelled by phase oppositions developed in said paths of predetermined differing delaying time duration.
Claim 24
Dependent Claim
33 words
The method of claim 19 further including the steps of: driving each of said n amplifiers with equal excitation signals; and terminating each active element in said amplifiers with an optimum load impedance.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1994-12-02 | 1995-06-03 | 1995-12-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-12-02 | 1999-06-03 | 1999-12-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-12-02 | 2003-06-03 | 2003-12-03 | $7700.00 | Window Closed / Lapsed |