Semiconductor memory device

Claim 2

A semiconductor integrated circuit device comprising: a first node for receiving a first voltage; a second node for receiving a second voltage smaller than the first voltage; word lines; a pair of data lines; memory cells of static type coupled to the word lines and the pair of data lines so that each memory cell is coupled to one word line and the pair of data lines; a variable impedance circuit coupled between the first node and the pair of data lines and controlled such that its impedance becomes relatively high when the device is in a data write-in mode in comparison with its impedance in a data read-out mode, the variable impedance circuit including: a first pair of P-channel MOSFETs in which the source-drain paths thereof are coupled between the first node and the pair of data lines, respectively, and the gates thereof are coupled to the second node, whereby the first pair of P-channel MOSFETs are turned on in response to the application of the first and second voltages to the first and second nodes, respectively, and a second pair of P-channel MOSFETs in which the source-drain paths thereof are coupled between the first node and the pair of data lines, respectively, and the gates thereof are coupled to receive a control signal, whereby the second pair of P-channel MOSFETs are turned on in the data read-out mode and turned off in the data write-in mode; a data input circuit which is activated in the data write-in mode and which includes means for changing a level of either one of the pair of data lines to a level substantially equal to the second voltage; a data output circuit which is activated in the data read-out mode; a pair of write data lines coupled to outputs of the data input circuit; a pair of read data lines coupled to inputs of the data output circuit; a first pair of N-channel MOSFETs for coupling the data input circuit to the pair of data lines via the pair of write data lines in the data write-in mode; and a third pair of P-channel MOSFETs for coupling the data output circuit to the pair of data lines via the pair of read data lines in the data read-out mode.

Claim 3

A semiconductor integrated circuit device according to claim 1, wherein each memory cell includes: a pair of MOSFETs each one having its gate and drain cross-coupled to the drain and gate of the other one of said pair of MOSFETs, respectively, a pair of load elements respectively coupled to the drains of the pair of MOSFETs and a pair of transfer gate MOSFETs, each transfer gate MOSFET having its source-drain path coupled between the drain of a respective one of the pair of MOSFETs and a respective one of the pair of data lines, and the gates of both transfer gate MOSFETs are coupled to one of the word lines.

Claim 4

A semiconductor integrated circuit device according to claim 2, wherein the load elements include resistors of polycrystalline silicon.

Claim 5

A semiconductor integrated circuit device according to claim 3, wherein the semiconductor integrated circuit device is a bipolar - CMOS type memory device.

Claim 6

A semiconductor integrated circuit device according to claim 4, wherein the bipolar - CMOS type memory device is compatible with emitter coupled logic.

Claim 7

A semiconductor integrated circuit device according to claim 3, wherein the first pair of P-channel MOSFETs of said variable impedance circuit have conductances smaller than that of the second pair of P-channel MOSFETs thereof.

Claim 8

A semiconductor integrated circuit according to claim 6, wherein the second voltage is of a potential more negative than the first voltage.

Claim 9

A semiconductor integrated circuit according to claim 7, wherein the first voltage is substantially at ground potential.

Claim 10

A semiconductor integrated circuit according to claim 8, wherein the pair of MOSFETs that are cross-coupled and pair of transfer gate MOSFETs of each memory cell are N-channel MOSFETs.

Claim 11

A semiconductor integrated circuit according to claim 1, wherein the second voltage is of a potential more negative and of greater magnitude than the first voltage.

Claim 12

A semiconductor memory device on a substrate comprising: a first node for receiving a first voltage; a second node for receiving a second voltage smaller than the first voltage; a plurality of word lines; a plurality of pairs of complementary data lines; a plurality of static memory cells coupled to the plurality of word lines and the plurality of pairs of complementary data lines so that each static memory is coupled to one word line and one pair of complementary data lines; variable impedance circuits coupled between the first node and the plurality of pairs of complementary data lines so that each variable impedance circuit is coupled between the first node and one pair of complementary data lines, each one of the variable impedance circuits being selectively controlled so as to effect a change in impedance thereacross from a first value to a second value higher than the first value during a write-in mode of operation, each of the variable impedance circuits including: a first pair of P-channel MOSFETs in which the source-drain paths thereof are coupled between the first node and a corresponding pair of complementary data lines, respectively, and the gates thereof are coupled to the second node, whereby the first pair of P-channel MOSFETs are turned on in response to the application of the first and second voltages to the first and second nodes, respectively, and a second pair of P-channel MOSFETs in which the source-drain paths thereof are coupled between the first node and the corresponding pair of complementary data lines, respectively, and the gates thereof are coupled to receive a control signal, whereby the second pair of P-channel MOSFETs are turned on in the data read-out mode and turned off in the data write-in mode; a data input circuit which is activated in the data write-in mode and which includes means for changing a level of either one of the pair of data lines to a level substantially equal to the second voltage; a data output circuit which is activated in the data read-out mode; a pair of write data lines coupled to outputs of the data input circuit; a pair of read data lines coupled to inputs of the data output circuit; and a plurality of switching circuits coupled between the plurality of complementary data lines and the pair of data read and data write lines and each one thereof including: a first pair of N-channel MOSFETs for selectively coupling the data input circuit to a corresponding pair of complementary data lines via the pair of write data lines in the data write-in mode, and a third pair of P-channel MOSFETs for selectively coupling the corresponding pair of complementary data lines to the data output circuit via the pair of read data lines in the data read-out mode.

Claim 13

A semiconductor memory device on a substrate comprising: a first node for receiving a first voltage; a second node for receiving a second voltage smaller than the first voltage; a plurality of word lines; a plurality of pairs of complementary data lines; a plurality of static memory cells coupled to the plurality of word lines and the plurality of pairs of complementary data lines so that each static memory is coupled to one word line and one pair of complementary data lines; variable impedance circuits coupled between the first node and the plurality of pairs of complementary data lines so that each variable impedance circuit is coupled between the first node and one pair of complementary data lines, each one of the variable impedance circuits being selectively controlled so as to effect a change in impedance thereacross from a first value to a second value higher than the first value during a write-in mode of operation, each of the variable impedance circuits including: a first pair of P-channel MOSFETs in which the source-drain paths thereof are coupled between the first node and a corresponding pair of complementary data lines, respectively, and the gates thereof are coupled to the second node, whereby the first pair of P-channel MOSFETs are turned on in response to the application of the first and second voltages to the first and second nodes, respectively, and a second pair of P-channel MOSFETs in which the source-drain paths thereof are coupled between the first node and the corresponding pair of complementary data lines, respectively, and the gates thereof are coupled to receive a control signal, whereby the second pair of P-channel MOSFETs are turned on in the data read-out mode and turned off in the data write-in mode; a data input circuit which is activated in the data write-in mode and which includes means for changing a level of either one of the pair of data lines to a level substantially equal to the second voltage; a data output circuit which is activated in the data read-out mode; a pair of write data lines coupled to outputs of the data input circuit; a pair of read data lines coupled to inputs of the data output circuit; and a plurality of switching circuits coupled between the plurality of complementary data lines and the pair of data read and data write lines and each one thereof including: a first pair of N-channel MOSFETs for selectively coupling the data input circuit to a corresponding pair of complementary data lines via the pair of write data lines in the data write-in mode, and a third pair of P-channel MOSFETs for selectively coupling the corresponding pair of complementary data lines to the data output circuit via the pair of read data lines in the data read-out mode.

Claim 14

A semiconductor memory device according to claim 11, wherein each memory cell includes: a pair of MOSFETs each one having its gate and drain cross-coupled to the drain and gate of the other one of said pair of MOSFETs, respectively, a pair of load elements respectively coupled to the drains of said pair of MOSFETs thereof, and a pair of transfer gate MOSFETs, each transfer gate MOSFET having its source-drain path coupled between the drain of a respective one of the pair of MOSFETs of said memory cell and a respective one of a corresponding pair of data lines, and the gates of both transfer gate MOSFETs are coupled to one of said plurality of word lines.

Claim 15

A semiconductor memory device according to claim 12, wherein said load elements include resistors of polycrystalline silicon.

Claim 16

A semiconductor memory device according to claim 13, wherein the semiconductor memory device is a bipolar - CMOS type memory device.

Claim 17

A semiconductor memory device according to claim 14, wherein the bipolar - CMOS type memory device is compatible with emitter coupled logic.

Claim 18

A semiconductor memory device according to claim 14, wherein the second voltage is of a potential more negative than the first voltage.

Claim 19

A semiconductor memory device according to claim 16, wherein the first voltage is substantially at ground potential.

Claim 20

A semiconductor memory device according to claim 17, wherein the first pair of P-channel MOSFETs of said variable impedance circuit have conductances smaller than that of the second pair of P-channel MOSFETs thereof.

Claim 21

A semiconductor memory device according to claim 11, wherein the first pair of P-channel MOSFETs of said variable impedance circuit have conductances smaller than that of the second pair of P-channel MOSFETs thereof.

Claim 22

A semiconductor integrated circuit device comprising: a first node for receiving a first voltage; a second node for receiving a second voltage smaller than the first voltage; word lines; a pair of data lines; memory cells of static type coupled to the word lines and the pair of data lines so that each memory cell is coupled to one word line and the pair of data lines; a variable impedance circuit coupled between the first node and the pair of data lines and controlled such that its impedance becomes relatively high when the device is in a data write-in mode in comparison with its impedance in a data read-out mode, the variable impedance circuit including: a first pair of transistors, each one thereof having a main current path coupled between the first node and the pair of data lines, respectively, and a control terminal coupled to the second node, whereby the first pair of transistors are turned on in response to the application of the first and second voltages to the first and second node, respectively, and a second pair of transistors each one thereof having a main current path coupled between the first node and the pair of data lines, respectively, and a control terminal, the control terminals of the second pair of transistors being commonly coupled to receive a control signal, whereby the second pair of transistors are turned-on in the data read-out mode and turned off in the data write-in mode; a data input circuit which is activated in the data write-in mode and which includes means for changing a level of either one of the pair of data lines to a level substantially equal to the second voltage; a data output circuit which is activated in the data read-out mode; a pair of write data lines coupled to outputs of the data input circuit; a pair of read data lines coupled to inputs of the data output circuit; a first pair of MOSFETs for coupling the data input circuit to the path of data lines via the pair of write data lines in the data write-in mode; and a second pair of MOSFETs, of a complementary channel type to that of said first pair of MOSFETs, for coupling the data output circuit to the pair of data lines via the pair of read data lines in the data read-out mode.

Claim 23

A semiconductor integrated circuit device comprising: a first node for receiving a first voltage; a second node for receiving a second voltage smaller than the first voltage; word lines; a pair of data lines; memory cells of static type coupled to the word lines and the pair of data lines so that each memory cell is coupled to one word line and the pair of data lines; a variable impedance circuit coupled between the first node and the pair of data lines and controlled such that its impedance becomes relatively high when the device is in a data write-in mode in comparison with its impedance in a data read-out mode, the variable impedance circuit including: a first pair of transistors, each one thereof having a main current path coupled between the first node and the pair of data lines, respectively, and a control terminal coupled to the second node, whereby the first pair of transistors are turned on in response to the application of the first and second voltages to the first and second node, respectively, and a second pair of transistors each one thereof having a main current path coupled between the first node and the pair of data lines, respectively, and a control terminal, the control terminals of the second pair of transistors being commonly coupled to receive a control signal, whereby the second pair of transistors are turned-on in the data read-out mode and turned off in the data write-in mode; a data input circuit which is activated in the data write-in mode and which includes means for changing a level of either one of the pair of data lines to a level substantially equal to the second voltage; a data output circuit which is activated in the data read-out mode; a pair of write data lines coupled to outputs of the data input circuit; a pair of read data lines coupled to inputs of the data output circuit; a first pair of MOSFETs for coupling the data input circuit to the path of data lines via the pair of write data lines in the data write-in mode; and a second pair of MOSFETs, of a complementary channel type to that of said first pair of MOSFETs, for coupling the data output circuit to the pair of data lines via the pair of read data lines in the data read-out mode.

Claim 24

A semiconductor integrated circuit device according to claim 20, wherein the first pair of transistors of said variable impedance circuit, during conducting states thereof, have conductances smaller than that of the second pair of transistors thereof.

Claim 25

A semiconductor integrated circuit device according to claim 20, wherein each of the transistors of the first and second pair of transistors of said variable impedance circuit is a MOSFET in which the source-drain path and gate thereof are the main current path and control terminal thereof, respectively.

Claim 26

A semiconductor integrated circuit device according to claim 22, wherein the MOSFETs corresponding to the first pair and second pair of transistors are comprised of MOSFETs of the same channel type.

Claim 27

A semiconductor integrated circuit device according to claim 23, wherein the pair of MOSFETs for coupling the data input circuit to the pair of data lines includes N-channel MOSFETs and the pair of MOSFETs for coupling the data output circuit to the pair of data lines includes P-channel MOSFETs.

Claim 28

A semiconductor integrated circuit device according to claim 23, wherein the MOSFETs of the first pair and second pair of transistors are P-channel MOSFETs.

Claim 29

A semiconductor integrated circuit device according to claim 25, wherein the second voltage is of a potential more negative than the first voltage.

Claim 30

A semiconductor integrated circuit device according to claim 26, wherein the first voltage is substantially at ground potential.

Claim 31

A semiconductor integrated circuit device according to claim 27, wherein the semiconductor integrated circuit device is of a bipolar-CMOS type memory device.

Claim 32

A semiconductor integrated circuit device according to claim 27, wherein the MOSFETs of the first pair of transistors of said variable impedance circuit have conductances smaller than the MOSFETs of the second pair of transistors thereof.

Claim 33

A semiconductor integrated circuit device according to claim 20, wherein at least the first pair of transistors of said variable impedance circuit includes a pair of MOSFETs in which the source-drain path and gate thereof are the main current path and control terminal thereof, respectively.

Claim 34

A semiconductor integrated circuit device according to claim 30, wherein the MOSFETs of the first pair of transistors of the variable impedance circuit are P-channel MOSFETs.

Claim 35

A semiconductor integrated circuit device according to claim 30, wherein the second pair of transistors of said variable impedance circuit include bipolar transistors.

Claim 36

A semiconductor integrated circuit device according to claim 32, wherein the MOSFETs of the first pair of transistors of the variable impedance circuit are P-channel MOSFETs.

Claim 37

A semiconductor integrated circuit device according to claim 33, wherein the pair of MOSFETs for coupling the data input circuit to the pair of data lines includes N-channel MOSFETs and the pair of MOSFETs for coupling the data output circuit to the pair of data lines includes P-channel MOSFETs.

Claim 38

A semiconductor integrated circuit device according to claim 34, wherein the second voltage is of a potential more negative than the first voltage.

Claim 39

A semiconductor integrated circuit device according to claim 35, wherein the first voltage is substantially at ground potential.

Claim 40

A semiconductor memory device on a substrate comprising: a first node for receiving a first voltage; a second node for receiving a second voltage smaller than the first voltage; a plurality of word lines; a plurality of pairs of complementary data lines; a plurality of static memory cells coupled to the plurality of word lines and the plurality of pairs of complementary data lines so that each static memory cell is coupled to one word line and one pair of complementary data lines; variable impedance circuits coupled between the first node and the plurality of pairs of complementary data lines so that each variable impedance circuit is coupled between the first node and one pair of complementary data lines, each one of the variable impedance circuits being selectively controlled so as to effect a change in impedance thereacross from a first value to a second value higher than the first value during a write-in mode of operation, each of the variable impedance circuits including: a first pair of MOSFETs in which the source-drain paths thereof are coupled between the first node and a corresponding pair of complementary data lines, respectively, and the gates thereof are coupled to the second node, whereby the first pair of MOSFETs are turned on in response to the application of the first and second voltages to the first and second nodes, respectively, and a pair of transistors each one thereof having a main current path coupled between the first node and the corresponding pair of complementary data lines, respectively, and a control terminal, the control terminals of the pair of transistors being commonly coupled to receive a control signal, whereby the pair of transistors are turned on in the data read-out mode and turned off in the data write-in mode; a data input circuit which is activated in the data write-in node and which includes means for changing a level of either one of the pair of data lines to a level substantially equal to the second voltage; a data output circuit which is activated in the data read-out mode; a pair of write data lines coupled to outputs of the data input circuit; a pair of read data lines coupled to inputs of the data output circuit; and a plurality of switching circuits coupled between the plurality of complementary data lines and the pair of data read and data write lines and each one thereof including: a second pair of MOSFETs of a first channel type for selectively coupling the data input circuit to a corresponding pair of complementary data lines via the pair of write data lines in the data write-in mode; and a third pair of MOSFETs of a second, complementary channel type, for selectively coupling the corresponding pair of complementary data lines to the data output circuit via the pair of read data lines in the data read-out mode.

Claim 41

A semiconductor memory device on a substrate comprising: a first node for receiving a first voltage; a second node for receiving a second voltage smaller than the first voltage; a plurality of word lines; a plurality of pairs of complementary data lines; a plurality of static memory cells coupled to the plurality of word lines and the plurality of pairs of complementary data lines so that each static memory cell is coupled to one word line and one pair of complementary data lines; variable impedance circuits coupled between the first node and the plurality of pairs of complementary data lines so that each variable impedance circuit is coupled between the first node and one pair of complementary data lines, each one of the variable impedance circuits being selectively controlled so as to effect a change in impedance thereacross from a first value to a second value higher than the first value during a write-in mode of operation, each of the variable impedance circuits including: a first pair of MOSFETs in which the source-drain paths thereof are coupled between the first node and a corresponding pair of complementary data lines, respectively, and the gates thereof are coupled to the second node, whereby the first pair of MOSFETs are turned on in response to the application of the first and second voltages to the first and second nodes, respectively, and a pair of transistors each one thereof having a main current path coupled between the first node and the corresponding pair of complementary data lines, respectively, and a control terminal, the control terminals of the pair of transistors being commonly coupled to receive a control signal, whereby the pair of transistors are turned on in the data read-out mode and turned off in the data write-in mode; a data input circuit which is activated in the data write-in node and which includes means for changing a level of either one of the pair of data lines to a level substantially equal to the second voltage; a data output circuit which is activated in the data read-out mode; a pair of write data lines coupled to outputs of the data input circuit; a pair of read data lines coupled to inputs of the data output circuit; and a plurality of switching circuits coupled between the plurality of complementary data lines and the pair of data read and data write lines and each one thereof including: a second pair of MOSFETs of a first channel type for selectively coupling the data input circuit to a corresponding pair of complementary data lines via the pair of write data lines in the data write-in mode; and a third pair of MOSFETs of a second, complementary channel type, for selectively coupling the corresponding pair of complementary data lines to the data output circuit via the pair of read data lines in the data read-out mode.

Claim 42

A semiconductor memory device according to claim 37, wherein the first pair of MOSFETs of each variable impedance circuit are P-channel MOSFETs.

Claim 43

A semiconductor integrated circuit device according to claim 38, wherein the pair of transistors of each variable impedance circuit are comprised of bipolar transistors.

Claim 44

A semiconductor integrated circuit device according to claim 37, wherein the pair of transistors of each variable impedance circuit are comprised of bipolar transistors.

Claim 45

A semiconductor integrated circuit device according to claim 38, wherein the pair of MOSFETs for coupling the data input circuit to the pair of complementary data lines includes N-channel MOSFETs and the pair of MOSFETs for coupling the data output circuit to the pair of complementary data lines includes P-channel MOSFETs.

Claim 46

A semiconductor integrated circuit device according to claim 41, wherein the second voltage is of a potential more negative than the first voltage.

Claim 47

A semiconductor integrated circuit device according to claim 42, wherein the first voltage is substantially at ground potential.

Claim 48

A semiconductor integrated circuit device according to claim 43, wherein the pair of transistors of each variable impedance circuit are comprised of bipolar transistors.

Claim 49

A semiconductor integrated circuit device according to claim 37, wherein the first pair of MOSFETs of each variable impedance circuit have conductances smaller than that of the pair of transistors thereof.