Data reproducing circuit for memory system having an equalizer generating two different equalizing signals used for data reproduction

Claim 2

A data reproducing circuit for a memory system having a data sensing head, comprising: an equalizer, operatively connected to receive an analog signal from the data sensing head, varying an amplitude of said analog signal in accordance with a predetermined time, and generating first and second equalized signals from said analog signal, said equalizer including a delay circuit, first and second gain circuits and first and second differential amplifier circuits, said delay circuit and said first gain circuit being connected to a separate input terminal of said first differential amplifier, and said delay circuit and said second gain circuit being connected to a separate input terminal of said second differential amplifier circuit; and a digital data reproducing circuit, operatively connected to said equalizer, for receiving said first and second equalized signals, for differentiating said first equalized signal, for generating a window signal when and during a time said second equalized signal is greater than a predetermined threshold level, and for outputting a pulsed reproduction signal when said differentiated signal is greater than a predetermined level and said window signal exists.

Claim 3

A data reproducing circuit according to claim 1, wherein said equalizer comprises: a first equalizing signal generation circuit generating a first equalized signal f1 expressed by f1=f(t+τ)-K.sub.1 {f(t)+f(t+2τ)} where, f(t) is a signal sensed by said head, τ is a delay time, and k 1 is a first equalizing gain, and a second equalizing signal generation circuit generating a second equalized signal f 2 expressed by f2=f(t+τ)-k.sub.2 {f(t)+f(t+2τ)} where, k 2 is a second equalizing gain.

Claim 4

A data reproducing circuit according to claim 1, wherein said digital data reproducing circuit comprises: a differentiator, operatively connected to said equalizer, for receiving said first equalized signal and differentiating said first equalized signal by a predetermined differential constant; a window signal generation circuit, operatively connected to said equalizer, for receiving said second equalized signal and for generating a window signal when said second equalized signal is greater than said predetermined threshold level; and a pulse generation circuit, operatively connected to said differentiator and said window generation circuit, for generating said pulsed reproduction signal when said differential signal is greater than said predetermined level and said window signal exists.

Claim 5

A data reproducing circuit according to claim 1, wherein said digital data reproducing circuit comprises: a window signal generation circuit for discriminating a signal from the data sensing head and having an amplitude of a predetermined threshold value, for generating a window signal when the signal from the data sensing head is greater than said predetermined threshold valve; a selective differentiating circuit, operatively connected to said window signal generation circuit, for receiving said window signal, differentiating another signal corresponding to the signal to be discriminated and having an amplitude higher than an amplitude of the signal to be discriminated by a predetermined differentiating constant, and gating said differentiated signal by said window signal from said window signal generation circuit; and a pulse generation circuit, operatively connected to said selective differentiating circuit, for generating said pulsed reproduction signal when said gated differential signal is greater than a predetermined pulsing threshold level.

Claim 6

A data reproducing circuit for a memory system having a data sensing head, comprising: an equalizer, operatively connected to receive an analog signal from the data sensing head, varying an amplitude of said analog signal in accordance with a predetermined time, and generating first and second equalized signals for said analog signal, said equalizer comprising: a first equalizing signal generation circuit generating a first equalized signal f 1 expressed by f1=f(t+τ)-k.sub.1 {f(t)+f(t+2τ)} where, f(t) is a signal sensed by the data sensing head, τ is a delay time, and k 1 is a first equalizing gain, wherein said first equalizing signal generation circuit comprises: a first delay circuit, having an input terminal and an output terminal, operatively connected to receive said sensed signal and delaying said sensed signal by said delay time; a first gain circuit having an input terminal connected to the input terminal of said first delay circuit, having an output terminal, and having said first equalizing gain; and a first subtracting circuit having a first input terminal connected to the output terminal of said first delay circuit, and having a high input impedance, whereby the signal from said first delay circuit is reflected back to said first delay circuit, and having a second input terminal connected to the output terminal of said first gain circuit. said first delay circuit outputting said first delay signal f(t+τ) to the first input terminal of said first subtracting circuit and said second delay signal f(t+2τ), based upon said reflection signal from the first input terminal of said first subtracting circuit, to said input terminal of said first gain circuit, said first gain circuit outputting a signal of k 1 ·f(t) and k 1 ·f(t+2τ) to the second input terminal of said first subtracting circuit, and said first subtracting circuit subtracting the signal output from said first gain circuit from the signal output from said first delay circuit, to output said first equalized signal f1, and a second equalizing signal generation circuit generating a second equalized signal f2 expressed by f2=f(t+τ)-k.sub.2 {f(t)+f(t+2τ)} where, k 2 is a second equalizing gain, wherein said second equalizing signal generation circuit comprises: a second delay circuit having an input terminal and an output terminal, operatively connected to receive said sensed signal and delaying said sensed signal by said delay time; a second gain circuit having an input terminal connected to the input terminal of said second delay circuit, having an output terminal, and having said second equalizing gain; and a second subtracting circuit having a first input terminal connected to the output terminal of said second delay circuit, and having a high input impedance, whereby the signal from said second delay circuit is reflected back to said second delay circuit, and having a second input terminal connected to the output terminal of said second gain circuit, said second delay circuit outputting said third delayed signal f(t+τ) to the first input terminal of said second subtracting circuit and said fourth delay signal f(t+2τ), based upon said reflection signal from the first input terminal of said second subtracting circuit, to the input terminal of said second gain circuit, said second gain circuit outputting a signal of k 2 ·f(t) and k 2 ·f(t+2τ) to the second input terminal of said second subtracting circuit, and said second subtracting circuit subtracting the signal output from said second gain circuit from the signal output from said second delay circuit, to output said second equalized signal f2; and a digital data reproducing circuit, operatively connected to said equalizer, for receiving said first and second equalized signals, for differentiating said first equalized signal, for generating a window signal when and during a time said second equalized signal is greater than a predetermined threshold level, and for outputting a pulsed reproduction signal when said differentiated signal is greater than a predetermined level and said window signal exists.

Claim 7

A data reproducing circuit for a memory system having a data sensing head, comprising: an equalizer, operatively connected to receive an analog signal from the data sensing head, varying an amplitude of said analog signal in accordance with a predetermined time, and generating first and second equalized signals for said analog signal, said equalizer comprising: a first equalizing signal generation circuit generating a first equalized signal f 1 expressed by f1=f(t+τ)-k.sub.1 {f(t)+f(t+2τ)} where, f(t) is a signal sensed by the data sensing head, τ is a delay time, and k 1 is a first equalizing gain, wherein said first equalizing signal generation circuit comprises: a first delay circuit, having an input terminal and an output terminal, operatively connected to receive said sensed signal and delaying said sensed signal by said delay time; a first gain circuit having an input terminal connected to the input terminal of said first delay circuit, having an output terminal, and having said first equalizing gain; and a first subtracting circuit having a first input terminal connected to the output terminal of said first delay circuit, and having a high input impedance, whereby the signal from said first delay circuit is reflected back to said first delay circuit, and having a second input terminal connected to the output terminal of said first gain circuit. said first delay circuit outputting said first delay signal f(t+τ) to the first input terminal of said first subtracting circuit and said second delay signal f(t+2τ), based upon said reflection signal from the first input terminal of said first subtracting circuit, to said input terminal of said first gain circuit, said first gain circuit outputting a signal of k 1 ·f(t) and k 1 ·f(t+2τ) to the second input terminal of said first subtracting circuit, and said first subtracting circuit subtracting the signal output from said first gain circuit from the signal output from said first delay circuit, to output said first equalized signal f1, and a second equalizing signal generation circuit generating a second equalized signal f2 expressed by f2=f(t+τ)-k.sub.2 {f(t)+f(t+2τ)} where, k 2 is a second equalizing gain, wherein said second equalizing signal generation circuit comprises: a second delay circuit having an input terminal and an output terminal, operatively connected to receive said sensed signal and delaying said sensed signal by said delay time; a second gain circuit having an input terminal connected to the input terminal of said second delay circuit, having an output terminal, and having said second equalizing gain; and a second subtracting circuit having a first input terminal connected to the output terminal of said second delay circuit, and having a high input impedance, whereby the signal from said second delay circuit is reflected back to said second delay circuit, and having a second input terminal connected to the output terminal of said second gain circuit, said second delay circuit outputting said third delayed signal f(t+τ) to the first input terminal of said second subtracting circuit and said fourth delay signal f(t+2τ), based upon said reflection signal from the first input terminal of said second subtracting circuit, to the input terminal of said second gain circuit, said second gain circuit outputting a signal of k 2 ·f(t) and k 2 ·f(t+2τ) to the second input terminal of said second subtracting circuit, and said second subtracting circuit subtracting the signal output from said second gain circuit from the signal output from said second delay circuit, to output said second equalized signal f2; and a digital data reproducing circuit, operatively connected to said equalizer, for receiving said first and second equalized signals, for differentiating said first equalized signal, for generating a window signal when and during a time said second equalized signal is greater than a predetermined threshold level, and for outputting a pulsed reproduction signal when said differentiated signal is greater than a predetermined level and said window signal exists.

Claim 8

An equalizer according to claim 5, wherein said first delay circuit comprises a first inductor, and said second delay circuit comprises a second inductor, said first and second inductors defining said delay time.

Claim 9

A differentiator for a data reproducing circuit in a memory system having a data sensing head, comprising: a window signal generation circuit, operatively connected to the data sensing head, for discriminating a signal from the data sensing head and having an amplitude of a predetermined threshold to generate a window signal when said signal is greater than a predetermined threshold value; and a selective differentiating circuit, operatively connected to said window generation circuit, for receiving said window signal, differentiating another signal corresponding to said signal to be discriminated and having an amplitude higher than an amplitude of said window signal by a predetermined differentiating constant.

Claim 10

A differentiator for a data reproducing circuit in a memory system having a data sensing head, comprising: a window signal generation circuit, operatively connected to the data sensing head, for discriminating a signal from the data sensing head and having an amplitude of a predetermined threshold to generate a window signal when said signal is greater than a predetermined threshold value; and a selective differentiating circuit, operatively connected to said window generation circuit, for receiving said window signal, differentiating another signal corresponding to said signal to be discriminated and having an amplitude higher than an amplitude of said window signal by a predetermined differentiating constant.

Claim 11

A data reproducing circuit for a memory system having a data sensing head, comprising: an equalizer, operatively connected to receive an analog signal from the data sensing head, varying an amplitude of said analog signal in accordance with a predetermined time, and generating first and second equalized signals from said analog signal, said equalizer comprising: a first equalizing signal generation circuit generating a first equalized signal f1 expressed by f1=f(t+τ)-k.sub.1 {f(t)+f(t+2τ)} where, f(t) is a signal sensed by the data sensing head, τ is a delay time, and k 1 is a first equalizing gain, said first equalizing signal generation circuit comprising: a first delay circuit, operatively connected to said second equalizing signal generation circuit, for receiving said second equalized signal and delaying said sensed signal by said second equalized signal and having an input terminal and an output terminal; a first gain circuit having an input terminal connected to the input terminal of said first delay circuit and having said first equalizing gain and having an output terminal; and a first subtracting circuit having a first input terminal connected to the output terminal of said first delay circuit, and having a high input impedance, whereby the signal from said first delay circuit as reflected back to said first delay circuit, and having a second input terminal connected to the output terminal of said first gain circuit, said first delay circuit outputting a first delay signal f(t+τ) to the first input terminal of said first subtracting circuit and a second delay signal f(t+2τ), based upon said reflection signal input from said first input terminal of said first subtracting circuit, to the input terminal of said first gain circuit, said first gain circuit outputting a signal of k 1 ·f(t) and k 1 ·f(t+2τ) to the second input terminal of said first subtracting circuit, said first subtracting circuit subtracting the signal output from said first gain circuit from the signal output from said first delay circuit, and outputting said first equalized signal f1; a second equalizing signal generation circuit generating a second equalized signal f2 expressed by f2=f(t+τ)-k.sub.2 {f(t)+f(t+2τ)}, said second equalizing signal generation circuit comprising: a second delay circuit, operatively connected to said second equalizing signal generation circuit, for receiving said second signal and delaying said sensed signal by said delay and having an input terminal and an output terminal; a second gain circuit having an input terminal connected to the input terminal of said second delay circuit and having said second equalizing gain and having an output terminal; and a second subtracting circuit having a first input terminal connected to the output terminal of said second delay circuit, and having a high input impedance, whereby the signal from said second delay circuit is reflected back to said second delay circuit, and having a second input terminal connected to the output terminal of said second gain circuit, said second delay circuit outputting a third delayed signal f(t+τ) to the first input terminal of said second subtracting circuit and a fourth delay signal f(t+2τ), based upon said reflection signal from the first input terminal of said second subtracting circuit, to the input terminal of said second gain circuit, said second gain circuit outputting a signal of k 2 ·f(t) and k 2 ·f(t+2τ) to the second input terminal of said second subtracting circuit, and said second subtracting circuit subtracting the signal output from said second gain circuit from the signal output from said second delay circuit, and outputting said second equalized signal f2; a digital data reproducing circuit, operatively connected to said equalizer, for receiving said first and second equalized signals, for differentiating said first equalized signal, for generating a window signal when and during a time said second equalized signal is greater than a predetermined threshold level, and for outputting a pulsed reproduction signal when said differentiated signal is greater than a predetermined level and said window signal exists.

Claim 12

A data reproducing circuit for a memory system having a data sensing head, comprising: an equalizer, operatively connected to receive an analog signal from the data sensing head, varying an amplitude of said analog signal in accordance with a predetermined time, and generating first and second equalized signals from said analog signal, said equalizer comprising: a first equalizing signal generation circuit generating a first equalized signal f1 expressed by f1=f(t+τ)-k.sub.1 {f(t)+f(t+2τ)} where, f(t) is a signal sensed by the data sensing head, τ is a delay time, and k 1 is a first equalizing gain, said first equalizing signal generation circuit comprising: a first delay circuit, operatively connected to said second equalizing signal generation circuit, for receiving said second equalized signal and delaying said sensed signal by said second equalized signal and having an input terminal and an output terminal; a first gain circuit having an input terminal connected to the input terminal of said first delay circuit and having said first equalizing gain and having an output terminal; and a first subtracting circuit having a first input terminal connected to the output terminal of said first delay circuit, and having a high input impedance, whereby the signal from said first delay circuit as reflected back to said first delay circuit, and having a second input terminal connected to the output terminal of said first gain circuit, said first delay circuit outputting a first delay signal f(t+τ) to the first input terminal of said first subtracting circuit and a second delay signal f(t+2τ), based upon said reflection signal input from said first input terminal of said first subtracting circuit, to the input terminal of said first gain circuit, said first gain circuit outputting a signal of k 1 ·f(t) and k 1 ·f(t+2τ) to the second input terminal of said first subtracting circuit, said first subtracting circuit subtracting the signal output from said first gain circuit from the signal output from said first delay circuit, and outputting said first equalized signal f1; a second equalizing signal generation circuit generating a second equalized signal f2 expressed by f2=f(t+τ)-k.sub.2 {f(t)+f(t+2τ)}, said second equalizing signal generation circuit comprising: a second delay circuit, operatively connected to said second equalizing signal generation circuit, for receiving said second signal and delaying said sensed signal by said delay and having an input terminal and an output terminal; a second gain circuit having an input terminal connected to the input terminal of said second delay circuit and having said second equalizing gain and having an output terminal; and a second subtracting circuit having a first input terminal connected to the output terminal of said second delay circuit, and having a high input impedance, whereby the signal from said second delay circuit is reflected back to said second delay circuit, and having a second input terminal connected to the output terminal of said second gain circuit, said second delay circuit outputting a third delayed signal f(t+τ) to the first input terminal of said second subtracting circuit and a fourth delay signal f(t+2τ), based upon said reflection signal from the first input terminal of said second subtracting circuit, to the input terminal of said second gain circuit, said second gain circuit outputting a signal of k 2 ·f(t) and k 2 ·f(t+2τ) to the second input terminal of said second subtracting circuit, and said second subtracting circuit subtracting the signal output from said second gain circuit from the signal output from said second delay circuit, and outputting said second equalized signal f2; a digital data reproducing circuit, operatively connected to said equalizer, for receiving said first and second equalized signals, for differentiating said first equalized signal, for generating a window signal when and during a time said second equalized signal is greater than a predetermined threshold level, and for outputting a pulsed reproduction signal when said differentiated signal is greater than a predetermined level and said window signal exists.

Claim 13

A data reproducing circuit for a memory system having a data sensing head, comprising: an equalizer, operatively connected to receive an analog signal from the data sensing head, varying an amplitude of said analog signal in accordance with a predetermined time, and generating first and second equalized signals from said analog signal, said equalizer comprising: a first equalizing signal generation circuit generating a first equalized signal f1 expressed by f1=f(t+τ)-k.sub.1 {f(t)+f(t+2τ)} where, f(t) is a signal sensed by the data sensing head, τ is a delay time, and k 1 is a first equalizing gain, said first equalizing signal generation circuit comprising: a delay circuit having an input terminal and an output terminal, operatively connected to receive said sensed signal, for delaying said sensed signal by said delay time; a first gain circuit having an input terminal connected to the input terminal of said delay circuit having an output terminal and having said first equalizing gain; and a first subtracting circuit having a first input terminal connected to the output terminal of said delay circuit, and having a high input impedance, whereby the signal from said delay circuit is reflected back to said delay circuit, and having a second input terminal connected to the output terminal of said first gain circuit; and a second equalizing signal generation circuit generating a second equalized signal f 2 expressed by f2=f(t+τ)-k.sub.2 {f(t)+f(t+2τ)}, where k 2 is a second equalizing gain, said second equalizing signal generation circuit comprising: a second gain circuit, having an input terminal connected to the input terminal of said delay circuit, having an output terminal and having said second equalizing gain; and a second subtracting circuit having a first input terminal connected to the output terminal of said delay circuit, and having a second input terminal connected to the output terminal of said second gain circuit, said delay circuit outputting said first delayed signal f(t+τ) to the first input terminals of said first and second subtracting circuits, and said second delay signal f(t+2τ) based upon said reflection signal from the first input terminal of said first subtracting circuit, to the input terminals of said first and second gain circuits, said first gain circuit outputting a signal k 1 ·ft and k 1 ·f(t+2τ) to the second input terminal of said first subtracting circuit, said first subtracting circuit subtracting the signal output from said first gain circuit from the signal output from said first delay circuit, sand outputting said first equalizing signal f1, said second gain circuit outputting a signal of k 2 ·f(t) and k 2 ·f(t+2τ) to said second input terminal of said second subtracting circuit, said second subtracting circuit subtracting the signal output from said second gain circuit from the signal output from said delay circuit, and outputting said second equalized signal f2; a digital reproducing circuit, operatively connected to said equalizer, for receiving said first and second equalized signals, for differentiating said first equalized signal, for generating a window signal when and during a time said second equalized signal is greater than a predetermined threshold level, and for outputting a pulsed reproduction signal when said differentiated signal is greater than a predetermined level and said window signal exists.

Claim 14

A data reproducing circuit for a memory system having a data sensing head, comprising: an equalizer, operatively connected to receive an analog signal from the data sensing head, varying an amplitude of said analog signal in accordance with a predetermined time, and generating first and second equalized signals from said analog signal, said equalizer comprising: a first equalizing signal generation circuit generating a first equalized signal f1 expressed by f1=f(t+τ)-k.sub.1 {f(t)+f(t+2τ)} where, f(t) is a signal sensed by the data sensing head, τ is a delay time, and k 1 is a first equalizing gain, said first equalizing signal generation circuit comprising: a delay circuit having an input terminal and an output terminal, operatively connected to receive said sensed signal, for delaying said sensed signal by said delay time; a first gain circuit having an input terminal connected to the input terminal of said delay circuit having an output terminal and having said first equalizing gain; and a first subtracting circuit having a first input terminal connected to the output terminal of said delay circuit, and having a high input impedance, whereby the signal from said delay circuit is reflected back to said delay circuit, and having a second input terminal connected to the output terminal of said first gain circuit; and a second equalizing signal generation circuit generating a second equalized signal f 2 expressed by f2=f(t+τ)-k.sub.2 {f(t)+f(t+2τ)}, where k 2 is a second equalizing gain, said second equalizing signal generation circuit comprising: a second gain circuit, having an input terminal connected to the input terminal of said delay circuit, having an output terminal and having said second equalizing gain; and a second subtracting circuit having a first input terminal connected to the output terminal of said delay circuit, and having a second input terminal connected to the output terminal of said second gain circuit, said delay circuit outputting said first delayed signal f(t+τ) to the first input terminals of said first and second subtracting circuits, and said second delay signal f(t+2τ) based upon said reflection signal from the first input terminal of said first subtracting circuit, to the input terminals of said first and second gain circuits, said first gain circuit outputting a signal k 1 ·ft and k 1 ·f(t+2τ) to the second input terminal of said first subtracting circuit, said first subtracting circuit subtracting the signal output from said first gain circuit from the signal output from said first delay circuit, sand outputting said first equalizing signal f1, said second gain circuit outputting a signal of k 2 ·f(t) and k 2 ·f(t+2τ) to said second input terminal of said second subtracting circuit, said second subtracting circuit subtracting the signal output from said second gain circuit from the signal output from said delay circuit, and outputting said second equalized signal f2; a digital reproducing circuit, operatively connected to said equalizer, for receiving said first and second equalized signals, for differentiating said first equalized signal, for generating a window signal when and during a time said second equalized signal is greater than a predetermined threshold level, and for outputting a pulsed reproduction signal when said differentiated signal is greater than a predetermined level and said window signal exists.

Claim 15

A data reproducing circuit for a memory system having a data sensing head, comprising: an equalizer, operatively connected to receive an analog signal from the data sensing head, varying an amplitude of said analog signal in accordance with a predetermined time, and generating first and second equalized signals from said analog signals, said equalizer comprising: a first equalizing signal generation circuit generating a first equalized circuit f1 expressed by f1=f(t+τ)-k.sub.1 {f(t)+f(t+2τ)} where f(t) is a signal sensed by the data sensing head, τ is a delay time, and k 1 is a first equalizing gain, said first equalizing signal generation circuit comprising: a delay circuit having an input terminal and an output terminal, operatively connected to receive said sensed signal and delaying said sensed signal to said delay time; the first gain circuit having an input terminal connected to the input terminal of said delay circuit, having an output terminal, and having said first equalizing gain; a first subtracting circuit having a first input terminal connected to an output terminal of said delay circuit, and having a high input impedance, whereby the signal from said delay circuit is reflected back to said delay circuit, and having a second input terminal connected to an output terminal of said first gain circuit; and a second subtracting circuit having a first input terminal connected to the output terminal of said delay circuit, and having a second input terminal connected to the output terminal of said first gain circuit, said delay circuit outputting said first delayed signal f(t+τ) to the first input terminals of said first and second subtracting circuits, and said second delay signal f(t+2τ), based upon said reflection signal from the first input terminal of said first subtracting circuit, to the input terminals of said first and second gain circuits, said first gain circuit outputting a signal of k 1 ·f(t) and k 1 ·f(t+2τ) to the second input terminal of said first subtracting circuit, said first subtracting circuit subtracting the signal output from said first gain circuit from the signal output from said first delay circuit, to output of said first equalized signal f1; a second equalizing signal generation circuit generating a second equalized signal f2 expressed by f2=f(t+τ)-k.sub.2 {f(t)+f(t+2τ)} where k 2 is a second equalizing gain, said second equalizing signal generation circuit comprising: a second gain circuit having an input terminal connected to the input terminal of said delay circuit and having said second equalizing gain, said second gain circuit outputting a signal of k 2 ·f(t) and k 2 ·f(t+2τ) to the second input terminal of said second subtracting circuit, and said second subtracting circuit subtracting the signal output from said second gain circuit from the signal output from said delay circuit to output said second equalized signal f2; and a digital data reproducing circuit, operatively connected to said equalizer, for receiving said first and second equalized signals, for differentiating said first equalized signal, for generating a window signal when and during a time said second equalized signal is greater than a predetermined threshold level, and for outputting a pulsed reproduction signal when said differentiated signal is greater than a predetermined level and said window signal exists.

Claim 16

A data reproducing circuit for a memory system having a data sensing head, comprising: an equalizer, operatively connected to receive an analog signal from the data sensing head, varying an amplitude of said analog signal in accordance with a predetermined time, and generating first and second equalized signals from said analog signals, said equalizer comprising: a first equalizing signal generation circuit generating a first equalized circuit f1 expressed by f1=f(t+τ)-k.sub.1 {f(t)+f(t+2τ)} where f(t) is a signal sensed by the data sensing head, τ is a delay time, and k 1 is a first equalizing gain, said first equalizing signal generation circuit comprising: a delay circuit having an input terminal and an output terminal, operatively connected to receive said sensed signal and delaying said sensed signal to said delay time; the first gain circuit having an input terminal connected to the input terminal of said delay circuit, having an output terminal, and having said first equalizing gain; a first subtracting circuit having a first input terminal connected to an output terminal of said delay circuit, and having a high input impedance, whereby the signal from said delay circuit is reflected back to said delay circuit, and having a second input terminal connected to an output terminal of said first gain circuit; and a second subtracting circuit having a first input terminal connected to the output terminal of said delay circuit, and having a second input terminal connected to the output terminal of said first gain circuit, said delay circuit outputting said first delayed signal f(t+τ) to the first input terminals of said first and second subtracting circuits, and said second delay signal f(t+2τ), based upon said reflection signal from the first input terminal of said first subtracting circuit, to the input terminals of said first and second gain circuits, said first gain circuit outputting a signal of k 1 ·f(t) and k 1 ·f(t+2τ) to the second input terminal of said first subtracting circuit, said first subtracting circuit subtracting the signal output from said first gain circuit from the signal output from said first delay circuit, to output of said first equalized signal f1; a second equalizing signal generation circuit generating a second equalized signal f2 expressed by f2=f(t+τ)-k.sub.2 {f(t)+f(t+2τ)} where k 2 is a second equalizing gain, said second equalizing signal generation circuit comprising: a second gain circuit having an input terminal connected to the input terminal of said delay circuit and having said second equalizing gain, said second gain circuit outputting a signal of k 2 ·f(t) and k 2 ·f(t+2τ) to the second input terminal of said second subtracting circuit, and said second subtracting circuit subtracting the signal output from said second gain circuit from the signal output from said delay circuit to output said second equalized signal f2; and a digital data reproducing circuit, operatively connected to said equalizer, for receiving said first and second equalized signals, for differentiating said first equalized signal, for generating a window signal when and during a time said second equalized signal is greater than a predetermined threshold level, and for outputting a pulsed reproduction signal when said differentiated signal is greater than a predetermined level and said window signal exists.

Claim 17

An equalizer according to claim 10, wherein said delay circuit comprises an inductor defining said delay time.