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US5068701A Expired / Lapsed US ⏱️ 0.0 years remaining

Device for reading out quantities of electrical charge supplied by photodiodes having a semiconductor substrate

Assignee: Thales SA
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Filing: 1989-03-21
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Granted: 1991-11-26
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Expires: 2009-03-21
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Abstract

Abstract The invention concerns a device for reading quantities of electrical charge supplied by photodiodes. These photodiodes (1) are arranged at the intersections of rows and columns (4,5) of a matrix (area) array. The device consists of means (6) for storing charges coming from a row of column of the array during scanning, a shift register (10) having an input stage and n-1 intermediate stages, means (18, 20) for injecting bias charges into the receiving potential wells, and skimming type transfer means (19) for transferring the stored charges and bias charges towards the shift register. The readout during scanning of the charges form a row or column of photodiodes is obtained after n charge transfers and n-1 shift operations. With known devices, n readouts are carried out per row or column, making them very slow and/or inefficient with large or high-signal photodiodes.

Inventors

  • 👤 Pascal Prieur-Drevon

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 01:32
CPC Classifications
G; G11; G11C; G11C19/00; G11C19/28; G11C19/282; G11C19/285; G11C19/287

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 433 words
A device for reading out quantities of electrical charge supplied by photodiodes (1) having a semiconductor substrate and located at the intersections of rows and columns (4,5) in a matrix array, comprising an assembly (6), storage means (8) for creating storage potential wells in the substrate (2), each said storage potential well corresponding to a respective row or column and serving to store successively, row by row or column by column, charges coming from the respective photodiodes of each row or each column, a charge-coupled device shift register (10) having a semiconductor substrate (9) as well as control means for creating potential wells and transfer potentials in said shift register's substrate to convey electrical charges inside said register up to an output end (12) of said shift register, said end being coupled to means (13) for reading out quantities of charge, and, for each storage means (8), charge transfer means (16) having a semiconductor substrate (9), said charge transfer means having control means (18) for creating, in said substrate, transfer potentials and a receiving potential well for receiving charges contained in the corresponding storage potential well, said receiving potential wells of said transfer means (16) corresponding to the different storage potential wells that are also the potential wells of said shift register (10), and means (20) for injecting bias charges into said receiving potential wells, said control means of each transfer means (16) causing the transfer of bias charges contained in the receiving potential well of said transfer means to the corresponding storage potential well, and then the transfer of said bias charges and at least a part of said stored charges into the receiving potential well, characterized in that said shift register (10) has n successive stages for each photodiode (1), n-1 of these stages forming n-1 intermediate potential wells between, on the one hand, said receiving potential well corresponding to said photodiode and its neighboring photodiode in the same row or column, and on the other, a stage common to both the shift register (10) and said transfer means (16) corresponding to said photodiode and creating the said receiving potential well, the quantity of charge contained in each storage potential well being accounted for by said shift register (10) after n transfers of stored charges and bias charges towards said shift register, and n-1 shift operations, said charge injection means injecting bias charges into all of said shift register's receiving potential wells before each transfer of charge into said receiving potential wells, the quantity of charge to be read out for each photodiode being read after n transfers of stored charge.
Claim 2
Independent Claim 433 words
A device for reading out quantities of electrical charge supplied by photodiodes (1) having a semiconductor substrate and located at the intersections of rows and columns (4,5) in a matrix array, comprising an assembly (6), storage means (8) for creating storage potential wells in the substrate (2), each said storage potential well corresponding to a respective row or column and serving to store successively, row by row or column by column, charges coming from the respective photodiodes of each row or each column, a charge-coupled device shift register (10) having a semiconductor substrate (9) as well as control means for creating potential wells and transfer potentials in said shift register's substrate to convey electrical charges inside said register up to an output end (12) of said shift register, said end being coupled to means (13) for reading out quantities of charge, and, for each storage means (8), charge transfer means (16) having a semiconductor substrate (9), said charge transfer means having control means (18) for creating, in said substrate, transfer potentials and a receiving potential well for receiving charges contained in the corresponding storage potential well, said receiving potential wells of said transfer means (16) corresponding to the different storage potential wells that are also the potential wells of said shift register (10), and means (20) for injecting bias charges into said receiving potential wells, said control means of each transfer means (16) causing the transfer of bias charges contained in the receiving potential well of said transfer means to the corresponding storage potential well, and then the transfer of said bias charges and at least a part of said stored charges into the receiving potential well, characterized in that said shift register (10) has n successive stages for each photodiode (1), n-1 of these stages forming n-1 intermediate potential wells between, on the one hand, said receiving potential well corresponding to said photodiode and its neighboring photodiode in the same row or column, and on the other, a stage common to both the shift register (10) and said transfer means (16) corresponding to said photodiode and creating the said receiving potential well, the quantity of charge contained in each storage potential well being accounted for by said shift register (10) after n transfers of stored charges and bias charges towards said shift register, and n-1 shift operations, said charge injection means injecting bias charges into all of said shift register's receiving potential wells before each transfer of charge into said receiving potential wells, the quantity of charge to be read out for each photodiode being read after n transfers of stored charge.
Claim 3
Dependent Claim 46 words
Device according to claim 1, characterized in that said bias charge injection means (20) are parallel bias charge transfer means that inject equal quantities of bias charge into the respective receiving potential wells before each transfer of these bias charges towards the corresponding storage potential well.
Claim 4
Dependent Claim 93 words
Device according to claim 1, characterized in that said bias charge injection means are transfer means (17) that inject bias charges at one end of said shift register, said end being opposite to the readout end (12), so that by successive shift operations all the shift register's potential wells respectively contain equal quantities of bias charge before the first transfer of bias charges towards said storage potential wells, an extra quantity of bias charge being injected at the input end after each subsequent charge transfer from a storage well to a receiving well.
Claim 5
Dependent Claim 33 words
Device according to claim 1, characterized in that said photodiodes and storage means are of p-type semiconductor on an n-type semiconductor substrate (2), and said shift register has a p-type semiconductor substrate (9).
Claim 6
Dependent Claim 32 words
Device according to claim 1, characterized in that said photodiodes and storage means are of n-type semiconductor on an p-type semiconductor substrate, and said shift register has a p-type semiconductor substrate (9).

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1994-11-25 1995-05-27 1995-11-26 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1998-11-25 1999-05-27 1999-11-26 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2002-11-25 2003-05-27 2003-11-26 $7700.00 Window Closed / Lapsed

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