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US5068697A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor memory which is protected from erasure by light shields

Assignee: Sony Corp
•
Filing: 1990-07-17
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Granted: 1991-11-26
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Expires: 2010-07-17
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Abstract

Abstract A nonvolatile semiconductor memory device having memory cells in which a control gate is stacked on a floating gate through an insulating film. The memory device has redundant memory cells so as to compensate defective memory cells and a transistor to select the redundant memory cells and the redundant memory cells and the transistor to select the redundant memory cells are formed by a nonvolatile memory transistor. The transistor to select the redundant memory cells has a structure in which the upper surface and side walls of the floating gate are covered by a control gate or a structure in which the floating gate and control gate are covered by a light shielding film and an antireflection film formed under the light shielding film. In a nonvolatile semiconductor memory device having memory cells of a structure in which a control gate is stacked on a floating gate through an insulating film, a phosphosilicate glass film is formed on side walls of the floating gate and the control gate and a silicon nitride film and an arseno-silicate glass film or boro-phospho-silicide glass film are sequentially formed so as to cover the control gate.

Inventors

  • 👤 Masanori Noda
  • 👤 Akihiro Nakamura

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 23:31
CPC Classifications
H; H10; H10B; H10B69/00; H10D; H10D64/00; H10D64/01; H10D64/031; H10D64/035

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 112 words
A nonvolatile semiconductor memory device having memory cells in which a control gate is stacked on a floating gate through an insulating film, comprising: p1 a plurality of redundant memory cells for compensating defective memory cells; and a transistor for selecting said redundant memory cells, said redundant memory cells and said transistor for selecting said redundant memory cells formed by a nonvolatile memory transistor, and said transistor for selecting sad redundant memory cells having a structure in which a floating gate and a control gate are covered by an anti-reflection film which extends substantially beyond said floating and said control gates and a light shielding film formed over said light shielding film.
Claim 2
Dependent Claim 112 words
A nonvolatile semiconductor memory device having memory cells in which a control gate is stacked on a floating gate through an insulating film, comprising: p1 a plurality of redundant memory cells for compensating defective memory cells; and a transistor for selecting said redundant memory cells, said redundant memory cells and said transistor for selecting said redundant memory cells formed by a nonvolatile memory transistor, and said transistor for selecting sad redundant memory cells having a structure in which a floating gate and a control gate are covered by an anti-reflection film which extends substantially beyond said floating and said control gates and a light shielding film formed over said light shielding film.
Claim 3
Dependent Claim 25 words
A nonvolatile semiconductor memory device according to claim 1, wherein said light shielding film is formed of an aluminum film or an aluminum alloy film.
Claim 4
Dependent Claim 35 words
A nonvolatile semiconductor memory device according to claims 1 or 2, wherein said antireflection film is formed of a polycrystalline silicon film, a titanium nitride film, a metal silicide film, or an amorphous silicon film.
Claim 5
Dependent Claim 69 words
A nonvolatile semiconductor memory device having memory cells in which a control gate is stacked on a floating gate with an insulating film, between them comprising: a tapered phospho-silicate glass film is formed on the side walls of said floating gate and said control gate; and a silicon nitride film and an arseno-silicate glass film or a boro-phospho-silicate glass film sequentially formed so as to cover said control gate.
Claim 6
Dependent Claim 69 words
A nonvolatile semiconductor memory device having memory cells in which a control gate is stacked on a floating gate with an insulating film, between them comprising: a tapered phospho-silicate glass film is formed on the side walls of said floating gate and said control gate; and a silicon nitride film and an arseno-silicate glass film or a boro-phospho-silicate glass film sequentially formed so as to cover said control gate.
Claim 7
Dependent Claim 37 words
A nonvolatile semiconductor memory device according to claim 4, wherein contact holes for a source region and a drain region of a nonvolatile memory transistor are formed at locations which are spaced from said phospho-silicate glass film.

References Cited (Backward Citations)

US3967310A Cited
US4758869A Cited
US4847667A Cited
JPH0279477A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1994-11-25 1995-05-27 1995-11-26 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1998-11-25 1999-05-27 1999-11-26 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2002-11-25 2003-05-27 2003-11-26 $7700.00 Window Closed / Lapsed

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