US5067141A
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US
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Interpolator for varying a signal sampling rate
Assignee: InterDigital Technology Corp
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Filing: 1989-10-10
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Granted: 1991-11-19
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Expires: 2009-10-10
Abstract
Abstract An interpolator varies the sampling rate of a signal. The signal may comprise pairs of in-phase and quadrature components at a first rate which are serially input through a pair of memories connected in series. The serially connected memories operate at a second higher rate which is a multiple of the first rate. An output taps the signals being circulated by the serially connected memories which results in the output of a signal having the in-phase and quadrature components at the higher second rate.
Inventors
- 👤 David N. Critchlow
- 👤 Graham M. Avis
- 👤 Sandra J. K. Earlam
- 👤 Karle J. Johnson
- 👤 Bruce A. Smetana
- 👤 Gregory L. Westling
- 👤 Eric Paneth
- 👤 Moshe Yehushua
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:19
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/18; H04L27/22; H04L27/233; H04L27/2338; H03; H03D; H03D7/00; H03D7/16; H03D7/165; H03H; H03H17/00; H03H17/02; H03H17/06; H03H17/0621; H03H17/0635; H03H17/065; H03H17/0657; H03D2200/00; H03D2200/0041; H03D2200/005; H03D2200/0052; H03D2200/0054; H03D2200/0058; H03D2200/006; H03D2200/0062; H03D2200/0082; H03D3/00; H03D3/007; H03D7/161; H03H2218/00; H03H2218/04
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
148 words
An interpolator for varying the sampling rate of digital input signals having paired in-phase and quadrature components comprising; an input means for said input signals at a first sampling rate; a first memory for alternately storing the in-phase and quadrature components, said first memory being coupled to said input means and also being serially coupled to a second memory for alternately storing the quadrature and in-phase components; means to circulate said input signals through both of said memories at a second and increased sampling rate whereby each in-phase and quadrature component is circulated more than once through said memories before the next in-phase and quadrature pair of signals is input from said input means; and output means coupled with said memories which taps the circulation of signals circulated through the memories whereby the resultant output signal is a resampled and remultiplexed signal output at said second higher rate.
Claim 2
Dependent Claim
148 words
An interpolator for varying the sampling rate of digital input signals having paired in-phase and quadrature components comprising; an input means for said input signals at a first sampling rate; a first memory for alternately storing the in-phase and quadrature components, said first memory being coupled to said input means and also being serially coupled to a second memory for alternately storing the quadrature and in-phase components; means to circulate said input signals through both of said memories at a second and increased sampling rate whereby each in-phase and quadrature component is circulated more than once through said memories before the next in-phase and quadrature pair of signals is input from said input means; and output means coupled with said memories which taps the circulation of signals circulated through the memories whereby the resultant output signal is a resampled and remultiplexed signal output at said second higher rate.
Claim 3
Dependent Claim
43 words
The interpolator of claim 1 wherein means are included for weighting the resulting in-phase and quadrature output signals by filter coefficients, a digital-to-analog converter for converting said remultiplexed in-phase and quadrature output signals to analog signals, and means to integrate said analog signals.
Claim 4
Dependent Claim
185 words
An interpolator for varying the sampling rate of digital input signals of pairs of in-phase and quadrature components comprising: signal input means for providing said input signals at a first sampling rate; first and second serially connected memories, each for storing either as in-phase or quadrature component of said input signal; said first and second memories operable at a second higher rate which is a multiple X of said first rate; switch means associated with an input of said first memory for connecting said first memory with either said signal input means or serially with an output of said second memory such that a sample pair of in-phase and quadrature components is received from said signal input means by said first and second memories in series and is circulated between said first and second memories X times before the next pair of in-phase and quadrature components is received from said signal input means; and signal output means associated with said memories such that each in-phase and quadrature component is output X times in series whereby said sampling rate of the signal is increased X times.
Claim 5
Dependent Claim
185 words
An interpolator for varying the sampling rate of digital input signals of pairs of in-phase and quadrature components comprising: signal input means for providing said input signals at a first sampling rate; first and second serially connected memories, each for storing either as in-phase or quadrature component of said input signal; said first and second memories operable at a second higher rate which is a multiple X of said first rate; switch means associated with an input of said first memory for connecting said first memory with either said signal input means or serially with an output of said second memory such that a sample pair of in-phase and quadrature components is received from said signal input means by said first and second memories in series and is circulated between said first and second memories X times before the next pair of in-phase and quadrature components is received from said signal input means; and signal output means associated with said memories such that each in-phase and quadrature component is output X times in series whereby said sampling rate of the signal is increased X times.
Claim 6
Dependent Claim
46 words
An interpolator according to claim 3 wherein: said first rate is 320 kHz which equals a rate of 160 kHz pairs of in-phase and quadrature components; and said second rate is 1.6 MHz whereby X equals 5 and the resultant output sampling rate is 1.6 MHz.
Claim 7
Dependent Claim
43 words
The interpolator of claim 3 wherein means are included for weighting the resulting in-phase and quadrature output signals by filter coefficients, a digital-to-analog converter for converting said remultiplexed in-phase and quadrature output signals to analog signals, and means to integrate said analog signals.
Claim 8
Dependent Claim
180 words
An interpolator for varying the sampling rate of digital input signals having a plurality of sample components comprising: signal input means for providing said input signals at a first sampling rate; a plurality of serially connected memories, each for storing any one of said plurality of components of said input signal; said memories operable at a second higher rate which is a multiple X of said first rate; switch means associated with an input of a first of said memories for connecting said first memory with either said signal input means or serially with an output of the respective last memory of said serially connected memories such that a sample plurality of components is received from said signal input means by said memories in series and is circulated among said memories X times before the next sample plurality of components is received from said signal input means; and signal output means associated with said memories such that each of the plurality of components is output X times in series whereby said sampling rate of the signal is increased X times.
Claim 9
Dependent Claim
180 words
An interpolator for varying the sampling rate of digital input signals having a plurality of sample components comprising: signal input means for providing said input signals at a first sampling rate; a plurality of serially connected memories, each for storing any one of said plurality of components of said input signal; said memories operable at a second higher rate which is a multiple X of said first rate; switch means associated with an input of a first of said memories for connecting said first memory with either said signal input means or serially with an output of the respective last memory of said serially connected memories such that a sample plurality of components is received from said signal input means by said memories in series and is circulated among said memories X times before the next sample plurality of components is received from said signal input means; and signal output means associated with said memories such that each of the plurality of components is output X times in series whereby said sampling rate of the signal is increased X times.
Claim 10
Dependent Claim
27 words
An interpolator according to claim 6 wherein the input signal is a multiplexed signal having in-phase and quadrature components and two memories comprise said plurality of memories.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-11-18 | 1995-05-20 | 1995-11-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-11-18 | 1999-05-20 | 1999-11-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-11-18 | 2003-05-20 | 2003-11-19 | $7700.00 | Window Closed / Lapsed |