US5065335A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Decoding type select logic generating method
Assignee: Hitachi Ltd
•
Filing: 1989-03-15
•
Granted: 1991-11-12
•
Expires: 2009-03-15
Abstract
Abstract A decoding type select logic generating method includes the steps of listing on a group basis input signal names and output destination signal names contained in register transfer descriptions and control codes for commanding execution of the register transfers for each of the same input signal names and same output destination signal names, simplifying logics by replacing the control code having the hamming distance of one by a bit meaning "don't care" on the group basis, generating AND gates for the control codes and the input signal names in each of the groups having the same input signal name and combining the outputs of the AND gates, generating AND gates for the control codes in each group having the same output destination signal name and combining the outputs of the AND gates for each of the output destination signal names, and combining the outputs of the groups each having the same input signal name and the groups each having the same output destination signal name.
Inventors
- 👤 Takayoshi Yokota
- 👤 Keisuke Bekki
- 👤 Nobuhiro Hamada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 10:46
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
346 words
A decoding type select logic generating method, comprising the steps of: (a) listing groupwise input signal names and control codes contained in register transfer descriptions, respectively for each of the same input signal names; (b) performing bit comparison groupwise between said control codes of step (a) to thereby replace any bit of the control codes in a group in which the hamming distance is one by a code meaning "don't care" and retaining only one of said control codes as a valid control code when the comparison of said control codes shows coincidence as the result of said replacement; (c) generating an AND gate for each of said retained control codes, said AND gates producing output "1" in response to the input of the bit signals of said control code; (d) generating first AND gates by adding signal lines to the input of said AND gates, said signal lines corresponding to said input signal names, respectively: (e) generating a first OR gate receiving as inputs those output signals of said first AND gates having the same output destination signal name, respectively; (f) listing groupwise the output destination signal names contained in the register transfer descriptions and control codes for commanding execution of the register transfers, respectively, for each of the same output destination signal names; (g) performing bit comparison groupwise between said control codes of step (f) to thereby replace any bit of the control codes in a group in which the hamming distance is one by a code meaning "don't care" and retaining only one of said control codes as a valid control code when the comparison shows coincidence as the result of said replacement; (h) generating second AND gates for said control codes retained after step (g), said second AND gate producing output of "1" in response to the input of the bit signals of said control codes retained in step (g); and (i) generating a third AND gate receiving as inputs the outputs having the same output destination signal name from the outputs of said second AND gates and said first OR gate.
Claim 2
Dependent Claim
346 words
A decoding type select logic generating method, comprising the steps of: (a) listing groupwise input signal names and control codes contained in register transfer descriptions, respectively for each of the same input signal names; (b) performing bit comparison groupwise between said control codes of step (a) to thereby replace any bit of the control codes in a group in which the hamming distance is one by a code meaning "don't care" and retaining only one of said control codes as a valid control code when the comparison of said control codes shows coincidence as the result of said replacement; (c) generating an AND gate for each of said retained control codes, said AND gates producing output "1" in response to the input of the bit signals of said control code; (d) generating first AND gates by adding signal lines to the input of said AND gates, said signal lines corresponding to said input signal names, respectively: (e) generating a first OR gate receiving as inputs those output signals of said first AND gates having the same output destination signal name, respectively; (f) listing groupwise the output destination signal names contained in the register transfer descriptions and control codes for commanding execution of the register transfers, respectively, for each of the same output destination signal names; (g) performing bit comparison groupwise between said control codes of step (f) to thereby replace any bit of the control codes in a group in which the hamming distance is one by a code meaning "don't care" and retaining only one of said control codes as a valid control code when the comparison shows coincidence as the result of said replacement; (h) generating second AND gates for said control codes retained after step (g), said second AND gate producing output of "1" in response to the input of the bit signals of said control codes retained in step (g); and (i) generating a third AND gate receiving as inputs the outputs having the same output destination signal name from the outputs of said second AND gates and said first OR gate.
Claim 3
Dependent Claim
77 words
A logic generating method according to claim 1, wherein when there are a plurality of retained control codes that differ from one another, said step of generating a first OR gate includes: (a) generating a third OR gate receiving as inputs the outputs of the plurality of said AND gates, one generated for each of said control codes; and (b) generating said first OR gate having an input supplied with the output of said third OR gate.
Claim 4
Dependent Claim
63 words
A logic generating method according to claim 1, further comprising the steps of: (a) counting the input signals to said AND gates and said OR gates; and (b) dividing said AND gates and said OR gates to generate an additional AND gate or to satisfying a constraint imposed on the number of said input signal lines, when said count exceeds a predetermined value.
Claim 5
Dependent Claim
63 words
A logic generating method according to claim 2, further comprising the steps of: (a) counting the input signals to said AND gates and said OR gates; and (b) dividing said AND gates and said OR gates to generate an additional AND gate or to satisfy a constraint imposed on the number of said input signal lines, when said count exceeds a predetermined value.
Claim 6
Dependent Claim
129 words
A logic generating method according to claim 1, further comprising the steps of: (a) storing and managing numbers of logic gate levels on a division basis for each of an input signal name select logic generating part, an output destination signal name select logic generating part and a wired logic generating part for completing a whole logic circuit by combining said input name select logic generating part and said output destination select logic part; (b) determining arithmetically said numbers of said logic gate levels in said whole logic circuit as a sum of said numbers of said logic gage levels in said logic generating parts; and (c) outputting said stored numbers of said logic gate levels and/or said calculated numbers of said logic gate levels onto an output apparatus.
Claim 7
Dependent Claim
128 words
A logic generating method according to claim 2, further comprising the steps of: (a) storing and managing numbers of logic gate levels on a division basis for each of an input signal name select logic generating part, an output destination signal name select logic generating part and wired logic generating part for completing a whole logic circuit by combining said input name select logic generating part and said output destination select logic part; (b) determining arithmetically said numbers of said logic gage levels in said whole logic circuit as a sum of said numbers of said logic gage levels in said logic generating parts; and (c) outputting said stored numbers of said logic gage levels and/or said calculated numbers of said logic gate levels onto an output apparatus.
Claim 8
Dependent Claim
128 words
A logic generating method according to claim 3, further comprising the steps of: (a) storing and managing numbers of logic gate levels on a division basis for each of an input signal name select logic generating part, an output destination signal name select logic generating part and a wired logic generating part for completing a whole logic circuit by combining said input name select logic generating part and said output destination select logic part; (b) determining arithmetically said numbers of said logic gage levels in said whole logic circuit as a sum of said numbers of said logic gage levels in said generating parts; and (c) outputting said stored numbers of said logic gage levels and/or said calculated numbers of said logic gate levels onto an output apparatus.
Claim 9
Dependent Claim
129 words
A logic generating method according to claim 4, further comprising the steps of: (a) storing and managing numbers of logic gate levels on a division basis for each of an input signal name select logic generating part, an output destination signal name select logic generating part and a wired logic generating part for completing a whole logic circuit by combining said input name select logic generating part and said output destination select logic part; (b) determining arithmetically said numbers of said logic gage levels in said whole logic circuit as a sum of said numbers of said logic gate levels in said logic generating parts; and (c) outputting said stored numbers of said logic gate levels and/or said calculated logic numbers of said logic gate levels an output apparatus.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-11-11 | 1995-05-13 | 1995-11-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-11-11 | 1999-05-13 | 1999-11-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-11-11 | 2003-05-13 | 2003-11-12 | $7700.00 | Window Closed / Lapsed |