US5065314A — Method and circuit for automatically communicatin…

Claim 1

Independent Claim 247 words

A method of communicating bytes of I/O data through a backbone between a backplane controller and an I/O module responsive to real time I/O data representing ON/OFF states of discrete I/O devices on a controlled machine or process, wherein the backplane controller includes means for generating a group of system I/O addresses to further generate a group of first backplane signals on the backplane that sequentially enable I/O modules in an I/O scan sequence to transfer bytes of real time I/O data between the backplane controller and the I/O modules, and wherein the backplane controller includes means for generating a second backplane signal in a first logic state and for generating the second backplane signal in a second logic state, the method comprising: the I/O module transferring to or from the backplane, in response to receiving one of the first backplane signals generated on the backplane and in response to receiving the second backplane signal generated in the first logic state, at least one byte of discrete, real time I/O data representing the ON/OFF states of the discrete I/O devices; and the I/O module transferring to or from the backplane, in response to receiving a second occurrence of the one of the first backplane signals and in response to receiving the second backplane signal generated in the second logic state, a file of I/O data including I/O data indicating conditions for the discrete I/O devices that are distinguishable from the ON/OFF states of the discrete I/O devices.

Claim 2

Independent Claim 247 words

A method of communicating bytes of I/O data through a backbone between a backplane controller and an I/O module responsive to real time I/O data representing ON/OFF states of discrete I/O devices on a controlled machine or process, wherein the backplane controller includes means for generating a group of system I/O addresses to further generate a group of first backplane signals on the backplane that sequentially enable I/O modules in an I/O scan sequence to transfer bytes of real time I/O data between the backplane controller and the I/O modules, and wherein the backplane controller includes means for generating a second backplane signal in a first logic state and for generating the second backplane signal in a second logic state, the method comprising: the I/O module transferring to or from the backplane, in response to receiving one of the first backplane signals generated on the backplane and in response to receiving the second backplane signal generated in the first logic state, at least one byte of discrete, real time I/O data representing the ON/OFF states of the discrete I/O devices; and the I/O module transferring to or from the backplane, in response to receiving a second occurrence of the one of the first backplane signals and in response to receiving the second backplane signal generated in the second logic state, a file of I/O data including I/O data indicating conditions for the discrete I/O devices that are distinguishable from the ON/OFF states of the discrete I/O devices.

Claim 3

Dependent Claim 115 words

The method of claim 1, wherein the step of transferring the byte of discrete I/O data is carried out in response to receiving the one of the first backplane signals that is generated in response to a system I/O address which is generated for the I/O module during the I/O scan sequence; and wherein the step of transferring the file of I/O data is carried out in response to receiving the second backplane signal generated in response to a system-level programming instruction for file transfer that includes a system I/O address that is the same as the system I/O address for which the byte of discrete I/O data is transferred during the I/O scan sequence.

Claim 4

Dependent Claim 134 words

The method of claim 1, wherein the byte of discrete real time I/O data is associated with a first system I/O address; wherein the file of I/O data is associated with a second system I/O address; wherein generating the second backplane signal in the first logic state is in response to generation of the first system I/O address, wherein generating the second backplane signal in the second logic state is in response to generation of the second system I/O address; wherein the I/O module transfers, in response to the generation of the first system I/O address, the byte of real time I/O data representing the ON/OFF states of the discrete I/O devices; and wherein the I/O module transfers, in response to the generation of the second system I/O address, the file of I/O data.

Claim 5

Dependent Claim 231 words

A backplane interface circuit for interfacing an I/O module to a backplane, wherein the I/O module is responsive to discrete I/O data representing ON/OFF states of discrete I/O devices on a controlled machine or process, and wherein the I/O module is responsive to a module enable signal on the backplane to transfer a byte of discrete I/O data to or from the backplane, the backplane interface circuit comprising: byte transfer means for storing and transferring a byte of discrete I/O data which, during operation, is transferred to or from the backplane in a byte transfer mode; file transfer means for storing and transferring a file of I/O data which, during operation, is transferred to or from the backplane in a file transfer mode; a backplane enable circuit with logic means responsive to the module enable signal generated on the backplane to enable the backplane interface circuit for transfer of I/O data, the backplane enable circuit also including decoding and enabling means responsive to a second backplane signal received from the backplane in a first logic state for enabling the byte transfer means to transfer a byte of I/O data to or from the backplane; and wherein the decoding and enabling means is responsive to the second backplane signal in a second logic state for enabling the file transfer means to transfer the file of I/O data to or from the backplane.

Claim 6

Dependent Claim 231 words

A backplane interface circuit for interfacing an I/O module to a backplane, wherein the I/O module is responsive to discrete I/O data representing ON/OFF states of discrete I/O devices on a controlled machine or process, and wherein the I/O module is responsive to a module enable signal on the backplane to transfer a byte of discrete I/O data to or from the backplane, the backplane interface circuit comprising: byte transfer means for storing and transferring a byte of discrete I/O data which, during operation, is transferred to or from the backplane in a byte transfer mode; file transfer means for storing and transferring a file of I/O data which, during operation, is transferred to or from the backplane in a file transfer mode; a backplane enable circuit with logic means responsive to the module enable signal generated on the backplane to enable the backplane interface circuit for transfer of I/O data, the backplane enable circuit also including decoding and enabling means responsive to a second backplane signal received from the backplane in a first logic state for enabling the byte transfer means to transfer a byte of I/O data to or from the backplane; and wherein the decoding and enabling means is responsive to the second backplane signal in a second logic state for enabling the file transfer means to transfer the file of I/O data to or from the backplane.

Claim 7

Dependent Claim 29 words

The backplane interface circuit of claim 4, wherein the byte transfer means, the file transfer means, and the decoding and enabling means are included in a single integrated circuit.

Claim 8

Dependent Claim 43 words

The backplane interface circuit of claim 4, wherein the file of I/O data transferred to or from the backplane is a file of data indicating conditions for the discrete I/O devices that are distinguishable from the ON/OFF state of the discrete I/O devices.

Claim 9

Dependent Claim 148 words

The backplane interface circuit of claim 4, wherein the discrete I/O data is associated with a first system I/O address; wherein the file of I/O data is associated with a second system I/O address; wherein the decoding and enabling means includes means for recognizing the second backplane signal in the first logic state as a first byte address signal generated in response to the first system I/O address; wherein the decoding and enabling means includes means for recognizing the second backplane signal in the second logic state as a second byte address signal generated in response to the second system I/O address; wherein the decoding and enabling means responds to the first byte address signal to enable transfer of the byte of discrete I/O data; and wherein the decoding and enabling means responds to the second byte address signal to enable transfer of the file of I/O data.

Claim 10

Dependent Claim 236 words

An integrated circuit for I/O modules of programmable controllers for communicating through a data bus a file of I/O data representing conditions related to discrete I/O devices on a controlled machine or process, the integrated circuit comprising: first data transfer circuitry for storing and exchanging real time I/O data representing ON/OFF states of the discrete I/O devices; second data transfer circuitry for storing and exchanging a file of I/O data indicating conditions which are distinguishable from the ON/OFF state of the discrete I/O devices; and an enabling circuit connected for enabling the first data transfer circuitry, the enabling circuit being connected during operation to an I/O module enable line to receive a first enabling signal, and the enabling circuit being responsive to the first enabling signal to enable a byte of real time I/O data representing ON/OFF states of the discrete I/O devices to be transferred between the data bus and the first data transfer circuitry; and wherein the enabling circuit is also connected for enabling the second data transfer circuitry, the enabling circuit being connected during operation to the I/O module enable line to receive the first enabling signal and to a second enabling line to receive a second enabling signal and wherein the enabling circuit is responsive to the first and second enabling signals to enable the file of I/O data to be transferred between the data bus and the second data transfer circuitry.

Claim 11

Dependent Claim 236 words

An integrated circuit for I/O modules of programmable controllers for communicating through a data bus a file of I/O data representing conditions related to discrete I/O devices on a controlled machine or process, the integrated circuit comprising: first data transfer circuitry for storing and exchanging real time I/O data representing ON/OFF states of the discrete I/O devices; second data transfer circuitry for storing and exchanging a file of I/O data indicating conditions which are distinguishable from the ON/OFF state of the discrete I/O devices; and an enabling circuit connected for enabling the first data transfer circuitry, the enabling circuit being connected during operation to an I/O module enable line to receive a first enabling signal, and the enabling circuit being responsive to the first enabling signal to enable a byte of real time I/O data representing ON/OFF states of the discrete I/O devices to be transferred between the data bus and the first data transfer circuitry; and wherein the enabling circuit is also connected for enabling the second data transfer circuitry, the enabling circuit being connected during operation to the I/O module enable line to receive the first enabling signal and to a second enabling line to receive a second enabling signal and wherein the enabling circuit is responsive to the first and second enabling signals to enable the file of I/O data to be transferred between the data bus and the second data transfer circuitry.

Claim 12

Dependent Claim 227 words

An integrated circuit for I/O modules of programmable controllers and responsive to signals generated by a backplane controller for communicating two types of I/O data through a backplane data bus on a backplane, the integrated circuit comprising: first means for receiving an I/O module enable signal generated through the backplane in response to decoding of an I/O module address by the backplane controller; wherein the first means includes second means for receiving first byte address signals and second byte address signals generated through the backplane in response to operation of the backplane controller; wherein said second means generates first enable signals in response to the first byte address signals and said second means generates second enable signals in response to the second byte address signals; third means coupled to the second means for enabling a first byte of real time I/O data representing ON/OFF states of a group of discrete I/O devices to be communicated over the backplane data bus in response to receiving the first enable signals from the second means; and fourth means coupled to the second means for enabling a second byte of I/O data representing conditions about one discrete I/O device which are distinguishable from the ON/OFF state of the discrete I/O device to be communicated over the backplane data bus in response to receiving the second enable signals from the second means.

Claim 13

Dependent Claim 227 words

An integrated circuit for I/O modules of programmable controllers and responsive to signals generated by a backplane controller for communicating two types of I/O data through a backplane data bus on a backplane, the integrated circuit comprising: first means for receiving an I/O module enable signal generated through the backplane in response to decoding of an I/O module address by the backplane controller; wherein the first means includes second means for receiving first byte address signals and second byte address signals generated through the backplane in response to operation of the backplane controller; wherein said second means generates first enable signals in response to the first byte address signals and said second means generates second enable signals in response to the second byte address signals; third means coupled to the second means for enabling a first byte of real time I/O data representing ON/OFF states of a group of discrete I/O devices to be communicated over the backplane data bus in response to receiving the first enable signals from the second means; and fourth means coupled to the second means for enabling a second byte of I/O data representing conditions about one discrete I/O device which are distinguishable from the ON/OFF state of the discrete I/O device to be communicated over the backplane data bus in response to receiving the second enable signals from the second means.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1994-11-11	1995-05-13	1995-11-12	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1998-11-11	1999-05-13	1999-11-12	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2002-11-11	2003-05-13	2003-11-12	$7700.00	Window Closed / Lapsed

Method and circuit for automatically communicating in two modes through a backplane

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