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US5062005A Expired / Lapsed US ⏱️ 0.0 years remaining

Videodisc reproducing apparatus

Assignee: Panasonic Holdings Corp
•
Filing: 1989-02-01
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Granted: 1991-10-29
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Expires: 2009-02-01
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Abstract

Abstract A videodisc reproducing apparatus includes a pilot carrier extraction circuit for extracting a pilot carrier from a videodisc reproduced signal and a clock generating circuit. The clock generating circuit includes an analog/digital converter and a phase-locked loop oscillator for generating a sampling clock signal for the analog/digital converter, whereby the videodisc reproduced signal is converted into digital form in synchronism with the pilot carrier. A phase-shift circuit is provided for phase shifting the sampling clock signal and for applying a thus phase-shifted sampling clock signal to the analog/digital converter. A phase detecting circuit is provided for detecting a digital sampling phase of a synchronizing signal included in a MUSE signal of the videodisc reproduced signal which has been converted into digital form according to positional information in the synchronizing signal of the videodisc reproduced signal detected by a synchronizing signal detection circuit. The phase detecting circuit further detects whether the detected digital sampling phase is advanced or retarded with respect to a digital sampling phase of a specified normal MUSE signal. An up/down counter is provided for generating an address signal output according to an output of the phase detecting circuit to control the phase-shift circuit.

Inventors

  • 👤 Hiromu Kitaura
  • 👤 Yoshio Hirauchi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 12:30
CPC Classifications
H; H04; H04N; H04N9/00; H04N9/79; H04N9/87; H04N9/89; H04N9/797

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 269 words
A videodisc reproducing apparatus comprising: a pilot carrier extraction circuit for extracting a pilot carrier from a videodisc reproduced signal; a clock generating circuit comprising an analog/digital converter and a phase-locked loop oscillator for generating a sampling clock signal for said analog/digital converter by which said videodisc reproduced signal is converted into digital form in synchronism with said pilot carrier; a phase-shift circuit for phase shifting said sampling clock signal for providing a plurality of phases of said sampling clock signal, and for applying a thus phase shifted sampling clock signal to said analog/digital converter, said phase shift circuit comprising a combination of a plurality of fine phase-delay circuits; a synchronizing signal detection circuit for detecting a synchronizing signal included in a MUSE signal of said videodisc reproduced signal converted into digital form by said analog/digital converter; a phase detecting circuit for detecting a digital sampling phase of said synchronization signal included in said MUSE signal of said videodisc reproduced signal converted into a digital form by said analog/digital converter according to positional information in said synchronizing signal detected by said synchronizing signal detection circuit, and for detecting whether a thus detected digital sampling phase is advanced or retarded with respect to a digital sampling phase of a specified normal MUSE signal; and an address generating circuit for generating an address signal output, said address generating circuit comprising an up/down counter controlled by an output of said phase detecting circuit, wherein an optimum sampling phase of said sampling clock signal is constantly attained by controlling said phase-shift circuit according to said address signal output from said address generating circuit.
Claim 2
Dependent Claim 269 words
A videodisc reproducing apparatus comprising: a pilot carrier extraction circuit for extracting a pilot carrier from a videodisc reproduced signal; a clock generating circuit comprising an analog/digital converter and a phase-locked loop oscillator for generating a sampling clock signal for said analog/digital converter by which said videodisc reproduced signal is converted into digital form in synchronism with said pilot carrier; a phase-shift circuit for phase shifting said sampling clock signal for providing a plurality of phases of said sampling clock signal, and for applying a thus phase shifted sampling clock signal to said analog/digital converter, said phase shift circuit comprising a combination of a plurality of fine phase-delay circuits; a synchronizing signal detection circuit for detecting a synchronizing signal included in a MUSE signal of said videodisc reproduced signal converted into digital form by said analog/digital converter; a phase detecting circuit for detecting a digital sampling phase of said synchronization signal included in said MUSE signal of said videodisc reproduced signal converted into a digital form by said analog/digital converter according to positional information in said synchronizing signal detected by said synchronizing signal detection circuit, and for detecting whether a thus detected digital sampling phase is advanced or retarded with respect to a digital sampling phase of a specified normal MUSE signal; and an address generating circuit for generating an address signal output, said address generating circuit comprising an up/down counter controlled by an output of said phase detecting circuit, wherein an optimum sampling phase of said sampling clock signal is constantly attained by controlling said phase-shift circuit according to said address signal output from said address generating circuit.

References Cited (Backward Citations)

US4488170A Cited
US4672470A Cited
US4677499A Cited
US4733311A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1994-10-28 1995-04-29 1995-10-29 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1998-10-28 1999-04-29 1999-10-29 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2002-10-28 2003-04-29 2003-10-29 $7700.00 Window Closed / Lapsed

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