Circuit device for eliminating noise from an input signal independent of time of arrival of noise or noise width

Claim 2

A noise eliminating circuit comprising: first detecting means for continuously monitoring the logic level of an input signal by use of at least one first detecting element for detecting that the input signal is at a first logic level and detecting that the input signal has said first logic level within a predetermined operating cycle in accordance with the result of detecting by said first detecting element every said operating cycle; second detecting means for continuously monitoring the logic level of said input signal by use of at least one second detecting element for detecting that the input signal is at a second logic level and detecting that the input signal has said second logic level within said predetermined operating cycle in accordance with the result of detection by said second detecting element every said operating cycle; and output determining means coupled to said first and second detecting means for determining its output signal such that said output signal is at said first logic level in a first case where only said first detecting means continues its detecting over a predetermined time period longer than said operating cycle, said output signal is at said second logic level in a second case where only said second detecting means continues its detection over said predetermined time period, and said output signal is held at the logic level value that it had previously, when the input signal is not at said first logic level and not at said second logic level, including means for deciding the results of detection by said first and second detecting means every said operating cycle and determining said predetermined period according to the number of decisions made by said first and second detecting means.

Claim 3

A noise eliminating circuit comprising: first detecting means for continuously monitoring the logic level of an input signal by use of at least one first detecting element for detecting that the input signal is at a first logic level and detecting that the input signal has said first logic level within a predetermined operating cycle in accordance with the result of detection by said first detecting element every said operating cycle; second detecting means for continuously monitoring the logic level of said input signal by use of at least one second detecting element for detecting that the input signal is at a second logic level and detecting that the input signal has said second logic level within said predetermined operating cycle in accordance with the result of detection by said second detecting element every said operating cycle; and output determining means coupled to said first and second detecting means for determining its output signal such that said output signal is at said first logic level in a first case where only said first detecting means continues its detection over a predetermined time period longer than said operating cycle, said output signal is at said second logic level in a second case where only said second detecting means continues its detection over said predetermined time period, and said output signal is held at the logic level value that it had previously, when the input signal is not at said first logic level and not at said second logic level; wherein said first detecting means comprises a plurality of said first detecting elements to be operated alternately so that an interval in which all of said first detecting elements are not operated and may not be produced, in order to monitor said input signal continuously.

Claim 4

A noise eliminating circuit comprising: first detecting means for continuously monitoring the logic level of an input signal by use of at least one first detecting element for detecting that the input signal is at a first logic level and detecting that the input signal has said first logic level within a predetermined operating cycle in accordance with the result of detection by said first detecting element every said operating cycle; second detecting means for continuously monitoring the logic level of said input signal by use of at least one second detecting element for detecting that the input signal is at a second logic level and detecting that the input signal has said second logic level within said predetermined operating cycle in accordance with the result of detection by said second detecting element every said operating cycle; and output determining means coupled to said first and second detecting means for determining its output signal such that said output signal is at said first logic level in a first case where only said first detecting means continues its detection over a predetermined time period longer than said operating cycle, said output signal is at said second logic level in a second case where only said second detecting means continues its detection over said predetermined time period, and said output signal is held at the logic level value that it had previously, when the input signal is not at said first logic level and not at said second logic level; wherein said first detecting means comprises a plurality of said first detecting elements to be operated alternately so that an interval in which all of said first detecting elements are not operated and may not be produced, in order to monitor said input signal continuously.

Claim 5

A noise eliminating circuit according to claim 2, in which said first detecting elements are reset periodically in said predetermined operating cycle.

Claim 6

A noise eliminating circuit according to claim 3, in which said first detecting means includes at least one latch means for holding the result of detection by at least one of said first detecting elements.

Claim 7

A noise eliminating circuit according to claim 2, in which operating periods of said first detecting elements are overlapped.

Claim 8

A noise eliminating circuit comprising: first detecting means for continuously monitoring the logic level of an input signal by use of at least one first detecting element for detecting that the input signal is at a first logic level and detecting that the input signal has said first logic level within a predetermined operating cycle in accordance with the result of detection by said first detecting element every said operating cycle; second detecting means for continuously monitoring the logic level of said input signal by use of at least one second detecting element for detecting that the input signal is at a second logic level and detecting that the input signal has said second logic level within said predetermined operating cycle in accordance with the result of detection by said second detecting element every said operating cycle; and output determining means coupled to said first and second detecting means for determining its output signal such that said output signal is at said first logic level in a first case where only said first detecting means continues its detection over a predetermined time period longer than said operating cycle, said output signal is at said second logic level in a second case where only said second detecting means continues its detection over said predetermined time period, and said output signal is held at the logic level value that it had previously, when the input signal is not at said first logic level and not at said second logic level; wherein said second detecting means comprises a plurality of said second detecting elements to be operated alternately so that an interval in which all of said second detecting elements are not operated and may not be produced, in order to monitor said input signal continuously.

Claim 9

A noise eliminating circuit comprising: first detecting means for continuously monitoring the logic level of an input signal by use of at least one first detecting element for detecting that the input signal is at a first logic level and detecting that the input signal has said first logic level within a predetermined operating cycle in accordance with the result of detection by said first detecting element every said operating cycle; second detecting means for continuously monitoring the logic level of said input signal by use of at least one second detecting element for detecting that the input signal is at a second logic level and detecting that the input signal has said second logic level within said predetermined operating cycle in accordance with the result of detection by said second detecting element every said operating cycle; and output determining means coupled to said first and second detecting means for determining its output signal such that said output signal is at said first logic level in a first case where only said first detecting means continues its detection over a predetermined time period longer than said operating cycle, said output signal is at said second logic level in a second case where only said second detecting means continues its detection over said predetermined time period, and said output signal is held at the logic level value that it had previously, when the input signal is not at said first logic level and not at said second logic level; wherein said second detecting means comprises a plurality of said second detecting elements to be operated alternately so that an interval in which all of said second detecting elements are not operated and may not be produced, in order to monitor said input signal continuously.

Claim 10

A noise eliminating circuit according to claim 6, in which said second detecting elements are reset periodically in said predetermined operating cycle.

Claim 11

A noise eliminating circuit according to claim 7, in which said second detecting means includes at least one latch means for holding the result of detection by at least one of said second detecting elements.

Claim 12

A noise eliminating circuit according to claim 6, in which operating periods of said second detecting elements are overlapped.

Claim 13

A noise eliminating circuit comprising: first detecting means for continuously and alternately monitoring the logic level of an input signal by use of a plurality of first detecting elements for detecting that the input signal is at a first logic level and detecting that the input signal has said first logic level within a predetermined operating cycle in accordance with the results of detection by said first detecting elements every said operating cycle; second detecting means for continuously and alternately monitoring the logic level of said input signal by use of a plurality of second detecting elements for detecting that the input signal is at a second logic level distinct from said first logic level and detecting that the input signal has said second logic level within said predetermined operating cycle in accordance with the results of detection by said second detecting elements every said operating cycle; and output determining means coupled to said first and second detecting means for determining its output signal such that said output signal is at said first logic level in a first case where only said first detecting means continues its detection over a plurality of said operating cycles, said output signal is at said second logic level in a second case where only said second detecting means continues its detection over a plurality of said operating cycles, and said output signal is held at the logic level that it had previously, when the input signal is not at said first logic level and not at said second logic level.

Claim 14

A noise eliminating circuit comprising: first detecting means for continuously and alternately monitoring the logic level of an input signal by use of a plurality of first detecting elements for detecting that the input signal is at a first logic level and detecting that the input signal has said first logic level within a predetermined operating cycle in accordance with the results of detection by said first detecting elements every said operating cycle; second detecting means for continuously and alternately monitoring the logic level of said input signal by use of a plurality of second detecting elements for detecting that the input signal is at a second logic level distinct from said first logic level and detecting that the input signal has said second logic level within said predetermined operating cycle in accordance with the results of detection by said second detecting elements every said operating cycle; and output determining means coupled to said first and second detecting means for determining its output signal such that said output signal is at said first logic level in a first case where only said first detecting means continues its detection over a plurality of said operating cycles, said output signal is at said second logic level in a second case where only said second detecting means continues its detection over a plurality of said operating cycles, and said output signal is held at the logic level that it had previously, when the input signal is not at said first logic level and not at said second logic level.

Claim 15

A noise eliminating circuit according to claim 10, in which said first and second detecting elements are reset periodically in said predetermined operating cycle.

Claim 16

A noise eliminating circuit according to claim 11, in which said first and second detecting means include latch means for holding the result of detection by at least one of said first and second detecting elements.

Claim 17

A noise eliminating circuit according to claim 10, in which operating periods of said first and second detecting elements are overlapped.

Claim 18

A noise eliminating circuit according to claim 10, in which said output determining means includes means for deciding the results of detection by said first and second detecting means every said operating cycle and determining said predetermined period according to a number of results of detection made by said first and second detecting means.

Claim 19

A noise eliminating circuit comprising: first detecting means for continuously monitoring the logic level of an input signal by use of a pair of reset-set latch means which are reset in a predetermined operating cycle and operated alternately to latch a first logic level of the input signal, a latch means for temporarily latching an output of one of said pair of reset-set latch means and a logical means for logically combining outputs of the other of said pair of reset-set latch means and said latch means and detecting that the input signal has said first logic level within said operating cycle in response to the result of latch by said pair of reset-set latch means every said operating cycle; second detecting means for continuously monitoring the logic level of the input signal by use of a pair of reset-set latch means which are reset in said predetermined operating cycle and operated alternately to latch a second logic level of the input signal, a latch means for temporarily latching an output of one of said pair of reset-set latch means and a logical means for logically combining outputs of the other of said pair of reset-set latch means and said latch means and detecting that the input signal has said second logic level within said operating cycle in response to the result of latch by said pair of reset-set latch means every said operating cycle; and output determining means coupled to said first and second detecting means for determining its output signal such that said output signal is at said first logic level in a first case where only said first detecting means continues its detection over a plurality of said operating cycles, said output signal is at said second logic level in a second case where only said second detecting means continues its detection over a plurality of said operating cycles, and said output signal is held at the logic level that it had previously, when the input signal is not at said first logic level and not at said second logic level.

Claim 20

A noise eliminating circuit comprising: first detecting means for continuously monitoring the logic level of an input signal by use of a pair of reset-set latch means which are reset in a predetermined operating cycle and operated alternately to latch a first logic level of the input signal, a latch means for temporarily latching an output of one of said pair of reset-set latch means and a logical means for logically combining outputs of the other of said pair of reset-set latch means and said latch means and detecting that the input signal has said first logic level within said operating cycle in response to the result of latch by said pair of reset-set latch means every said operating cycle; second detecting means for continuously monitoring the logic level of the input signal by use of a pair of reset-set latch means which are reset in said predetermined operating cycle and operated alternately to latch a second logic level of the input signal, a latch means for temporarily latching an output of one of said pair of reset-set latch means and a logical means for logically combining outputs of the other of said pair of reset-set latch means and said latch means and detecting that the input signal has said second logic level within said operating cycle in response to the result of latch by said pair of reset-set latch means every said operating cycle; and output determining means coupled to said first and second detecting means for determining its output signal such that said output signal is at said first logic level in a first case where only said first detecting means continues its detection over a plurality of said operating cycles, said output signal is at said second logic level in a second case where only said second detecting means continues its detection over a plurality of said operating cycles, and said output signal is held at the logic level that it had previously, when the input signal is not at said first logic level and not at said second logic level.

Claim 21

A noise eliminating circuit according to claim 15, in which operating periods of said pair of reset-set latch means of each of said first and second detecting elements are overlapped.

Claim 22

A noise eliminating circuit according to claim 15, in which said output determining means includes means for deciding the results of detection by said first and second detecting means every said operating cycle and determining said plurality of operating cycles according to the number of decisions made by said first and second detecting means.