US5057699A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Switch interface for determining position of a plurality of switches using a determined time
Assignee: SUMMIT COMMERICAL/GILBERLTAR CORP
•
Filing: 1989-12-20
•
Granted: 1991-10-15
•
Expires: 2009-12-20
Abstract
Abstract A circuit for interfacing switches to a component which allows the positions of the switches to be determined by the component. The component includes an input port and an output port. A switch network which is a parallel combination of two or more series combinations of a resistor and a switch is connected between the input and output port. A capacitor is connected between the input port and ground. The component determines switch positions by outputting a voltage on the output port and determining the time for the capacitor to charge to a predetermined value. Since each series combination has a unique resistance, the position of the switches therein can be determined in accordance with the capacitor charging time.
Inventors
- 👤 James W. Spence
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 16:07
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/042; G05B19/0423; H; H03; H03M; H03M11/00; H03M11/22; H03M11/24; G05B2219/00; G05B2219/20; G05B2219/21; G05B2219/21006
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
145 words
A switch interface, comprising: a first port for selectively outputting a lower and a higher voltage; a second port; a plurality of series combinations of a switch and a resistor which are connected in a parallel circuit, each of said plurality of series combinations having a unique resistance and each of said switches being in an open or closed position, said parallel circuit having a first node connected to said first port and a second node connected to said second port; a capacitor connected between said second port and a node biased at a reference voltage; means for determining a time for a voltage at said second port to increase to a predetermined voltage level when said first port changes state from said lower voltage to said higher voltage; and means for determining said position of each of said switches in accordance with said time.
Claim 2
Dependent Claim
145 words
A switch interface, comprising: a first port for selectively outputting a lower and a higher voltage; a second port; a plurality of series combinations of a switch and a resistor which are connected in a parallel circuit, each of said plurality of series combinations having a unique resistance and each of said switches being in an open or closed position, said parallel circuit having a first node connected to said first port and a second node connected to said second port; a capacitor connected between said second port and a node biased at a reference voltage; means for determining a time for a voltage at said second port to increase to a predetermined voltage level when said first port changes state from said lower voltage to said higher voltage; and means for determining said position of each of said switches in accordance with said time.
Claim 3
Dependent Claim
105 words
The switch interface as claimed in claim 1, further comprising: a plurality of ports for selectively outputting a lower and a higher voltage; for each of said plurality of ports for selectively outputting a lower and a higher voltage, a plurality of series combinations of a switch and a resistor which are connected in parallel, each of said plurality of series combinations having a unique resistance and each of said switches being in an open or closed position, said parallel circuit having a first node connected to said port for selectively outputting one of two voltages and a second node connected to said second port.
Claim 4
Dependent Claim
15 words
The switch interface as claimed in claim 1, wherein said reference voltage node is grounded.
Claim 5
Dependent Claim
25 words
The switch interface as claimed in claim 1, wherein a Nth series combination in said plurality of series combinations has a resistance equal to R/2.sup.(N-1).
Claim 6
Dependent Claim
63 words
The switch interface as claimed in claim 1, wherein said plurality of switches are interfaced to a digital component wherein said first port initially outputs a LOW voltage and said second port is initially biased at said reference voltage, said component outputting a HIGH voltage at said first port when said position of each of said plurality of switches is to be determined.
Claim 7
Dependent Claim
15 words
The switch interface as claimed in claim 5, wherein said digital component is a microcontroller.
Claim 8
Dependent Claim
20 words
The switch interface as claimed in claim 5, wherein said digital component includes an internal timer to determine said time.
Claim 9
Dependent Claim
21 words
The switch interface as claimed in claim 5, wherein said predetermined voltage level is the switching threshold of said digital component.
Claim 10
Dependent Claim
58 words
The switch interface as claimed in claim 8, wherein said switching threshold is specified to be within a voltage range and said resistance of each of said plurality of series combinations is selected such that said voltage at said second port reaches said predetermined voltage at a unique range of times for each possible combination of switch positions.
Claim 11
Dependent Claim
97 words
The switch interface as claimed in claim 5, wherein the potential of said first port is changed from said lower voltage to said higher voltage said means for determining a time determines the time, t 1 , for said voltage at said second port to switch from a LOW to a HIGH voltage and then the potential of said first port is changed from said higher voltage to said lower voltage and said means for determining a time determines the time for said voltage at said second port to switch from a HIGH to a LOW voltage.
Claim 12
Independent Claim
127 words
A method of interfacing a plurality of switches to a component such that the component can determine the positions of each individual switch, the component having an input and an output port initially biased at a LOW voltage, the switch interface having a parallel combination of a plurality of series combinations of a switch and a resistor, the parallel combination being connected between the input and output port, each series combination having a unique resistance, and a capacitor connected between the input port and a node biased at a reference voltage, comprising the steps of: outputting a HIGH voltage on the output port; determining the time for the capacitor to charge to a predetermined voltage; and determining the positions of the switches in accordance with the time.
Claim 13
Independent Claim
127 words
A method of interfacing a plurality of switches to a component such that the component can determine the positions of each individual switch, the component having an input and an output port initially biased at a LOW voltage, the switch interface having a parallel combination of a plurality of series combinations of a switch and a resistor, the parallel combination being connected between the input and output port, each series combination having a unique resistance, and a capacitor connected between the input port and a node biased at a reference voltage, comprising the steps of: outputting a HIGH voltage on the output port; determining the time for the capacitor to charge to a predetermined voltage; and determining the positions of the switches in accordance with the time.
Claim 14
Dependent Claim
19 words
The method as claimed in claim 11, wherein said predetermined voltage is the switching threshold of a digital component.
Claim 15
Independent Claim
150 words
A method of interfacing a plurality of switches to a component such that the component can determine the position of each individual switch, the component having an input and an output port initially biased at a LOW voltage. The switch interface having a parallel combination, of a plurality of series combinations of a switch and a resistor, the parallel combination being connected between the input and output port, each series combination having a unique resistance, and a capacitor connected between the input port and a node biased at a reference voltage, comprising the steps of: outputting a HIGH voltage on the output port; determining the time for the capacitor to charge to a predetermined level; outputting a LOW voltage on the output port; determining the time for the capacitor to discharge to a predetermined level; and determining the positions of the switches in accordance with the charging and discharging times.
Claim 16
Independent Claim
150 words
A method of interfacing a plurality of switches to a component such that the component can determine the position of each individual switch, the component having an input and an output port initially biased at a LOW voltage. The switch interface having a parallel combination, of a plurality of series combinations of a switch and a resistor, the parallel combination being connected between the input and output port, each series combination having a unique resistance, and a capacitor connected between the input port and a node biased at a reference voltage, comprising the steps of: outputting a HIGH voltage on the output port; determining the time for the capacitor to charge to a predetermined level; outputting a LOW voltage on the output port; determining the time for the capacitor to discharge to a predetermined level; and determining the positions of the switches in accordance with the charging and discharging times.
Claim 17
Dependent Claim
22 words
The method as claimed in claim 13, wherein the capacitor is allowed to fully charge between outputting the HIGH and LOW voltages.
Claim 18
Dependent Claim
19 words
The method as claimed in claim 13, wherein said predetermined level is the switching point of a digital component.
References Cited (Backward Citations)
US4306223A
Cited
US4190824A
Cited
DE2627206A1
Cited
US4315413A
Cited
US4488823A
Cited
USRE33119E
Cited
JPS61199321A
Cited
US4883991A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-14 | 1995-04-15 | 1995-10-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-14 | 1999-04-15 | 1999-10-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-14 | 2003-04-15 | 2003-10-15 | $7700.00 | Window Closed / Lapsed |