US5057694A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Optoelectronic relay circuit having charging path formed by a switching transistor and a rectifying diode
Assignee: Panasonic Electric Works Co Ltd
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Filing: 1990-03-06
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Granted: 1991-10-15
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Expires: 2010-03-06
Abstract
Abstract A semiconductor relay circuit includes an output FET connected to a diode array. The diode array generates a photovoltaic output in response to a light signal from a light emitting element. Across the drain and gate of the FET is a series circuit of a semiconductor device and a rectifier is connected, the switching transistor is being made conductive upon receipt at the diode array of the light signal and forms a charge current path for an accumulated charge across the gate and source of the FET. The rectifier restrains a photocurrent from reversely flowing between the drain and gate of the FET. Turning-on and turning-off operations of the relay circuit can be thereby made both achievable at a higher speed, and the reverse flow of the photocurrent upon the conduction of the output FET can be prevented from occurring.
Inventors
- 👤 Yukio Idaka
- 👤 Shuichiroh Yamaguchi
- 👤 Takeshi Matsumoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 06:13
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/78; H03K17/785; Y; Y10; Y10S; Y10S136/00; Y10S136/291; Y10S136/293
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
182 words
A semiconductor relay circuit comprising a light emitting means for generating a light signal, a diode array optically coupled to said light emitting means for generating a photovoltaic output in response to said light signal received, an output FET connected to said diode array for turning from a first impedance state to a second impedance state with an application of said photovoltaic output across a gate and a source of said output FET, an operation control means connected across the gate and source of said output FET, and a series circuit including a switching transistor and a rectifying diode connected across a drain and gate of said output FET, said switching transistor being turned to a low impedance state so as to form a charging path for an accumulated charge across the gate and source of said output FET when said diode array receives said light signal, and said rectifying diode preventing an reverse flow of a photocurrent across the gate and drain of said output FET when a voltage across the drain and source of said output FET becomes substantially zero.
Claim 2
Dependent Claim
182 words
A semiconductor relay circuit comprising a light emitting means for generating a light signal, a diode array optically coupled to said light emitting means for generating a photovoltaic output in response to said light signal received, an output FET connected to said diode array for turning from a first impedance state to a second impedance state with an application of said photovoltaic output across a gate and a source of said output FET, an operation control means connected across the gate and source of said output FET, and a series circuit including a switching transistor and a rectifying diode connected across a drain and gate of said output FET, said switching transistor being turned to a low impedance state so as to form a charging path for an accumulated charge across the gate and source of said output FET when said diode array receives said light signal, and said rectifying diode preventing an reverse flow of a photocurrent across the gate and drain of said output FET when a voltage across the drain and source of said output FET becomes substantially zero.
Claim 3
Dependent Claim
19 words
The circuit according to claim 1 wherein said operation controlling means includes a controlling FET of a depletion mode.
Claim 4
Dependent Claim
23 words
The circuit according to claim 1 wherein a resistor is connected in series with said switching transistor and diode of said series circuit.
Claim 5
Dependent Claim
19 words
The circuit according to claim 1 wherein said operation controlling means includes a controlling FET of a depletion mode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-14 | 1995-04-15 | 1995-10-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-14 | 1999-04-15 | 1999-10-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-14 | 2003-04-15 | 2003-10-15 | $7700.00 | Window Closed / Lapsed |