US5055803A
Expired / Lapsed
US
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Parameter tolerant PLL synthesizer
Assignee: Quarterhill Inc
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Filing: 1990-12-14
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Granted: 1991-10-08
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Expires: 2010-12-14
Abstract
Abstract In a PLL synthesizer, the tolerance to gain and component variations is greatly reduced when the gain of the loop in increased above that which the loop was initially designed for and if the third order loop symmetric ratio is reduced to a value within the range of 2.0 to 2.5. Higher order loops based on the third order symmetric ratio range have correspondingly lower transmission pole frequency to open unity gain frequency ratios.
Inventors
- 👤 Alexander W. Hietala
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 05:10
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/08; H03L7/085; H03L7/089; H03L7/0891; H03L7/093
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
130 words
A phase locked loop synthesizer having an open loop unity gain frequency and tolerance to component parameter variation, comprising: means for generating an output signal; means for producing a first signal related to a difference between said output signal and a predetermined reference signal; and means for modifying said first signal to produce a second signal coupled to said means for generating, said means for modifying including: (a) at least one filter transmission pole having a first break frequency related to the unity gain frequency by a first magnitude, (b) at least one filter transmission zero having a second break frequency related to the unity gain frequency by a second magnitude, and (c) a numeric value of one of said first magnitude and said second magnitude of 2.5 or less.
Claim 2
Dependent Claim
130 words
A phase locked loop synthesizer having an open loop unity gain frequency and tolerance to component parameter variation, comprising: means for generating an output signal; means for producing a first signal related to a difference between said output signal and a predetermined reference signal; and means for modifying said first signal to produce a second signal coupled to said means for generating, said means for modifying including: (a) at least one filter transmission pole having a first break frequency related to the unity gain frequency by a first magnitude, (b) at least one filter transmission zero having a second break frequency related to the unity gain frequency by a second magnitude, and (c) a numeric value of one of said first magnitude and said second magnitude of 2.5 or less.
Claim 3
Dependent Claim
26 words
A phase locked loop in accordance with claim 1 wherein said first break frequency is equal to said unity gain frequency multiplied by said first magnitude.
Claim 4
Dependent Claim
26 words
A phase locked loop in accordance with claim 1 wherein said second break frequency is equal to said unity gain frequency divided by said second magnitude.
Claim 5
Dependent Claim
23 words
A phase locked loop in accordance with claim 1 wherein said numeric value is in the range of values from 2.5 to 2.0.
Claim 6
Dependent Claim
35 words
A phase locked loop in accordance with claim 1 wherein said means for modifying further comprises(d) a numeric value of said other one of said first magnitude and said second magnitude of 2.5 or less.
Claim 7
Dependent Claim
20 words
A phase locked loop in accordance with claim 1 wherein said means for modifying further includes a fifth order filter.
Claim 8
Dependent Claim
35 words
A phase locked loop in accordance with claim 6 wherein said means for modifying further comprises(d) a numeric value of said other one of said first magnitude and said second magnitude of 7.84 or less.
Claim 9
Dependent Claim
31 words
A phase locked loop in accordance with claim 1 further comprising at least one current source having a current output value related to a predetermined value by a factor of 1.5.
Claim 10
Dependent Claim
174 words
A phase locked loop synthesizer having an open loop unity gain frequency and tolerance to component parameter variation, comprising: a voltage controlled oscillator producing an output signal; a frequency divider coupled to the output signal of the voltage controlled oscillator and producing a frequency-divided output signal; a phase detector coupled to the frequency divider and producing a control signal representing a difference between said frequency-divided output signal and a predetermined reference signal; a loop filter coupled to said phase detector to modify said control signal and coupling said modified control signal to said voltage controlled oscillator and further including: (a) at least one filter transmission pole having a first break frequency, (b) at least one filter transmission zero having a second break frequency, and (c) a first relationship between said first break frequency and the open loop unity gain frequency being equal to a first numeric value and a second relationship between said second break frequency and the open loop unity gain frequency being equal to a second numeric value of 2.5 or less.
Claim 11
Dependent Claim
174 words
A phase locked loop synthesizer having an open loop unity gain frequency and tolerance to component parameter variation, comprising: a voltage controlled oscillator producing an output signal; a frequency divider coupled to the output signal of the voltage controlled oscillator and producing a frequency-divided output signal; a phase detector coupled to the frequency divider and producing a control signal representing a difference between said frequency-divided output signal and a predetermined reference signal; a loop filter coupled to said phase detector to modify said control signal and coupling said modified control signal to said voltage controlled oscillator and further including: (a) at least one filter transmission pole having a first break frequency, (b) at least one filter transmission zero having a second break frequency, and (c) a first relationship between said first break frequency and the open loop unity gain frequency being equal to a first numeric value and a second relationship between said second break frequency and the open loop unity gain frequency being equal to a second numeric value of 2.5 or less.
Claim 12
Dependent Claim
26 words
A phase locked loop in accordance with claim 9 wherein said first break frequency is equal to said unity gain frequency multiplied by said first relationship.
Claim 13
Dependent Claim
26 words
A phase locked loop in accordance with claim 9 wherein said second break frequency is equal to said unity gain frequency divided by said second relationship.
Claim 14
Dependent Claim
23 words
A phase locked loop in accordance with claim 9 wherein said numeric value is in the range of values from 2.5 to 2.0.
Claim 15
Dependent Claim
18 words
A phase locked loop in accordance with claim 9 wherein said first numeric value is 2.5 or less.
Claim 16
Dependent Claim
19 words
A phase locked loop in accordance with claim 9 wherein said loop filter further includes a fifth order filter.
Claim 17
Dependent Claim
18 words
A phase locked loop in accordance with claim 14 wherein said first numeric value is 7.84 or less.
Claim 18
Dependent Claim
31 words
A phase locked loop in accordance with claim 9 further comprising at least one current source having a current output value related to a predetermined value by a factor of 1.5.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-07 | 1995-04-08 | 1995-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-07 | 1999-04-08 | 1999-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-07 | 2003-04-08 | 2003-10-08 | $7700.00 | Window Closed / Lapsed |