Brushless motor control system

Claim 2

In a brushless DC motor having a stator coil connected between a source of DC power voltage and circuit common and in which an alternating counter-emf exists, a circuit for converting stored inductive energy in said stator coil into useful motor mechanical energy, said circuit comprising: a) first switch means connected in series between said stator coil and said circuit common for selectively switching current through said stator coil to circuit common during a positive torque producing half-cycle of said alternating counter-emf, thereby maintaining a predetermined average value of said current, b) second switch means connected in series with a free-wheeling diode means across said stator coil for re-circulating said current through said stator coil when said first switch means is open and back-emf generated by said coil exceeds said counter-emf by an amount sufficient to forward-bias said diode means, whereby said current re-circulating through said stator coil results in positive torque while said first switch means is open, c) rotor position sensor means for generating a first plurality of control pulses for controlling operation of said second switch means responsive to positioning of a rotor of said DC motor, said control pulses being in synchronism with said alternating counter-emf, d) a pulse modulation circuit for generating a second plurality of control pulses, and e) a logic circuit for receiving said first and second plurality of control pulses and in response controlling operation of said first switch means in synchronism with said counter-emf.

Claim 3

The circuit of claim 1 wherein said first switch means is an n-channel depletion IGFET having a drain terminal connected to said stator coil, a source terminal connected to said circuit common, and a gate terminal connected to an output of said logic circuit.

Claim 4

The circuit of claim 1 wherein an anode of said diode means is connected to said stator coil and a cathode of said diode means is connected to said second switch means, and wherein said second switch means is a bipolar transistor having an emitter terminal connected to said source of DC power voltage, a collector terminal connected to said cathode, and a base terminal connected to said rotor position sensor means.

Claim 5

The circuit of claim 1 wherein said logic circuit is an AND gate.

Claim 6

The circuit of claim 1 wherein said pulse modulation circuit comprises a pulse width modulator for selectively controlling a width of pulses of said current through said stator coil and thereby maintaining said predetermined average value of said current.

Claim 7

The circuit of claim 1 wherein said pulse modulation circuit comprises a pulse rate modulator for selectively controlling a rate of pulses of said current through said stator coil and thereby maintaining said predetermined average value of said current.

Claim 8

The circuit of claim 1 wherein said pulse modulation circuit comprises circuitry for selectively controlling a number of pulses of said current through said stator coil during said positive torque producing half cycle and thereby maintaining said predetermined average value of said current.

Claim 9

The circuit of claim 1, wherein said switch means comprises transistors.

Claim 10

In a brushless DC motor having a stator coil connected between a source of DC power voltage and circuit common and in which an alternating counter-emf exists, a control circuit for minimizing ohmic power loss in said stator coil, said circuit comprising: a) switch means connected in series between said stator coil and said circuit common for alternately switching current through said stator coil to said circuit common and blocking current from flowing through said coil to said circuit common during a positive torque producing half-cycle of said alternating counter-emf, b) means for delaying said switching of said current by a first independently variable predetermined amount relative to onset of said half-cycle and advancing said blocking of said current by a second independently variable predetermined amount relative to the end of said half-cycle, thereby reducing current flow surges and consequently ohmic power loss through said stator coil at each successive onset and end of said half-cycle when said torque produced is low, c) rotor position sensor means for generating a first plurality of control pulses responsive to positioning of a rotor of said DC motor, said control pulses being in synchronism with said alternating counter-emf, d) a digital timing circuit for receiving said first plurality of control pulses and in response generating a second plurality of timing control pulses, e) a pulse modulation circuit for generating a third plurality of control pulses, and f) a logic circuit for receiving said second and third plurality of control pulses and in response controlling operation of said switch means in substantial synchronism with said counter-emf but with said switching and said blocking of said current delayed and advanced, respectively, by said first and second respective predetermined amounts.

Claim 11

In a brushless DC motor having a stator coil connected between a source of DC power voltage and circuit common and in which an alternating counter-emf exists, a control circuit for minimizing ohmic power loss in said stator coil, said circuit comprising: a) switch means connected in series between said stator coil and said circuit common for alternately switching current through said stator coil to said circuit common and blocking current from flowing through said coil to said circuit common during a positive torque producing half-cycle of said alternating counter-emf, b) means for delaying said switching of said current by a first independently variable predetermined amount relative to onset of said half-cycle and advancing said blocking of said current by a second independently variable predetermined amount relative to the end of said half-cycle, thereby reducing current flow surges and consequently ohmic power loss through said stator coil at each successive onset and end of said half-cycle when said torque produced is low, c) rotor position sensor means for generating a first plurality of control pulses responsive to positioning of a rotor of said DC motor, said control pulses being in synchronism with said alternating counter-emf, d) a digital timing circuit for receiving said first plurality of control pulses and in response generating a second plurality of timing control pulses, e) a pulse modulation circuit for generating a third plurality of control pulses, and f) a logic circuit for receiving said second and third plurality of control pulses and in response controlling operation of said switch means in substantial synchronism with said counter-emf but with said switching and said blocking of said current delayed and advanced, respectively, by said first and second respective predetermined amounts.

Claim 12

The circuit of claim 9 wherein said switch means is an n-channel depletion IGFET having a drain terminal connected to said stator coil, a source terminal connected to said circuit common, and a gate terminal connected to an output of said logic circuit.

Claim 13

The circuit of claim 9 wherein said logic circuit is an AND gate.

Claim 14

The circuit of claim 9 wherein said pulse modulation circuit comprises a pulse width modulator for selectively controlling the width of pulses of said current through said stator coil and thereby maintaining a predetermined average value of said current.

Claim 15

The circuit of claim 9 wherein said pulse modulation circuit comprises a pulse rate modulator for selectively controlling the rate of pulses of said current through said stator coil and thereby maintaining a predetermined average value of said current.

Claim 16

The circuit of claim 9 wherein said pulse modulation circuit comprises circuitry for selectively controlling the number of pulses of said current through said stator coil during said positive torque producing half cycle and thereby maintaining a predetermined average value of said current.

Claim 17

The circuit of claim 9 wherein said digital timing circuit comprises a microcontroller.

Claim 18

In a brushless DC motor having a stator coil connected between a source of DC power voltage and circuit common and in which an alternating counter-emf exists, a control circuit for minimizing ohmic power loss in said stator coil, said circuit comprising: a) switch means connected in series between said stator coil and said circuit common for alternately switching current through said stator coil to said circuit common and blocking current from flowing through said coil to said circuit common during a positive torque producing half-cycle of said alternating counter-emf, and b) means for delaying said switching of said current by a first independently variable predetermined amount relative to onset of said half-cycle and advancing said blocking of said current by a second independently variable predetermined amount relative to the end of said half-cycle, thereby reducing current flow surges and consequently ohmic power loss through said stator coil at each successive onset and end of said half-cycle when said torque produced is low, and said means for delaying comprising a digital timing circuit.

Claim 19

In a brushless DC motor having a stator coil connected between a source of DC power voltage and circuit common and in which an alternating counter-emf exists, a control circuit for minimizing ohmic power loss in said stator coil, said circuit comprising: a) switch means connected in series between said stator coil and said circuit common for alternately switching current through said stator coil to said circuit common and blocking current from flowing through said coil to said circuit common during a positive torque producing half-cycle of said alternating counter-emf, and b) means for delaying said switching of said current by a first independently variable predetermined amount relative to onset of said half-cycle and advancing said blocking of said current by a second independently variable predetermined amount relative to the end of said half-cycle, thereby reducing current flow surges and consequently ohmic power loss through said stator coil at each successive onset and end of said half-cycle when said torque produced is low, and said means for delaying comprising a digital timing circuit.

Claim 20

The circuit of claim 16 wherein said digital timing circuit comprises a microcontroller.

Claim 21

In a brushless DC motor having a stator coil connected between a source of DC power voltage and circuit common and in which an alternating counter-emf exists, a control circuit for minimizing ohmic power loss in said stator coil, said circuit comprising: a) switch means connected in series between said stator coil and said circuit common for alternately switching current through said stator coil to said circuit common and blocking current from flowing through said coil to said circuit common during a positive torque producing half-cycle of said alternating counter-emf, b) means for delaying said switching of said current by a first predetermined amount relative to onset of said half-cycle and advancing said blocking of said current by a second predetermined amount relative to the end of said half-cycle, thereby reducing current flow surges and consequently ohmic power loss through said stator coil at each successive onset and end of said half-cycle when said torque produced is low, c) rotor position sensor means for generating a first plurality of control pulses responsive to positioning of a rotor of said DC motor, said control pulses being in synchronism with said alternating counter-emf, d) a digital timing circuit for receiving said first plurality of control pulses and in response generating a second plurality of timing control pulses, e) a pulse modulation circuit for generating a third plurality of control pulses, and f) a logic circuit for receiving said second and third plurality of control pulses and in response controlling operation of said switch means in substantial synchronism with said counter-emf but with said switching and said blocking of said current delayed and advanced, respectively, by said first and second respective predetermined amounts.

Claim 22

In a brushless DC motor having a stator coil connected between a source of DC power voltage and circuit common and in which an alternating counter-emf exists, a control circuit for minimizing ohmic power loss in said stator coil, said circuit comprising: a) switch means connected in series between said stator coil and said circuit common for alternately switching current through said stator coil to said circuit common and blocking current from flowing through said coil to said circuit common during a positive torque producing half-cycle of said alternating counter-emf, b) means for delaying said switching of said current by a first predetermined amount relative to onset of said half-cycle and advancing said blocking of said current by a second predetermined amount relative to the end of said half-cycle, thereby reducing current flow surges and consequently ohmic power loss through said stator coil at each successive onset and end of said half-cycle when said torque produced is low, c) rotor position sensor means for generating a first plurality of control pulses responsive to positioning of a rotor of said DC motor, said control pulses being in synchronism with said alternating counter-emf, d) a digital timing circuit for receiving said first plurality of control pulses and in response generating a second plurality of timing control pulses, e) a pulse modulation circuit for generating a third plurality of control pulses, and f) a logic circuit for receiving said second and third plurality of control pulses and in response controlling operation of said switch means in substantial synchronism with said counter-emf but with said switching and said blocking of said current delayed and advanced, respectively, by said first and second respective predetermined amounts.

Claim 23

The circuit of claim 18 wherein said switch means is an n-channel depletion IGFET having a drain terminal connected to said stator coil, a source terminal connected to said circuit common, and a gate terminal connected to an output of said logic circuit.

Claim 24

The circuit of claim 18 wherein said logic circuit is an AND gate.

Claim 25

The circuit of claim 18 wherein said pulse modulation circuit comprises a pulse width modulator for selectively controlling a width of pulses of said current through said stator coil and thereby maintaining a predetermined average value of said current.

Claim 26

The circuit of claim 18 wherein said pulse modulation circuit comprises a pulse rate modulator for selectively controlling a rate of pulses of said current through said stator coil and thereby maintaining a predetermined average value of said current.

Claim 27

The circuit of claim 18 wherein said pulse modulation circuit comprises circuitry for selectively controlling a number of pulses of said current through said stator coil during said positive torque producing half cycle and thereby maintaining a predetermined average value of said current.

Claim 28

The circuit of claim 18 wherein said digital timing circuit comprises a microcontroller.