Method and apparatus for errorless switching

Claim 2

In a receiver, a method for errorless switching from a first digital signal comprising a first series of frames in which a first series of payloads is being transported in a first channel, to a second digital signal comprising a second series of frames in which a second series of payloads identical to said first series of payloads is being transported in a second channel, said second series of frames having starting locations, for particular ones of said second series of payloads, that can be different from starting locations of identical particular payloads, in said first series of frames, comprising the steps of: preprovisioning a first delay on said first channel such that said first channel has a total delay including said first delay greater than an actual delay of said second channel; aligning each frame of said first digital signal to a corresponding frame of said second digital signal so that each of said corresponding frames has a starting location for an identical particular payload from each of said first and second series of payloads; aligning said starting location and any subsequent locations of particular ones of said second series of payloads within said second series of frames to the starting location and any subsequent locations of identical particular ones of said first series of payloads within said first series of frames; making a determination to switch from said first digital signal to said second digital signal; and switching in response to said determination from said first digital signal to said second digital signal without loss of a single bit.

Claim 3

The method as defined in claim 1 wherein said step of aligning each frame includes the steps of: measuring the difference in delay between frames of said first digital signal and corresponding frames of said second digital signal; and adding a delay to said second channel equal to said measured difference in delay.

Claim 4

The method as defined in claim 2 wherein said step of measuring includes the step of determining to within a predetermined probability which frame of said first digital signal corresponds with a frame of said second digital signal.

Claim 5

The method as defined in claim 3 wherein said step of determining includes the steps of: a. obtaining a data pattern by reading a first predetermined number of data bytes from a predetermined location of a payload of a particular frame of said second digital signal; b. checking each payload of each successive frame of said first digital signal only at an identical predetermined location as was read in step (a) and counting each frame having a payload that is checked until a match to said data pattern is found or until a predetermined duration has passed; c. if a predetermined duration has passed going back to step (a) and repeating steps (a) through (c); d. if said match in step (b) is found obtaining said frame count which indicates a number of frames that said first digital signal is delayed behind said second digital signal; e. obtaining another data pattern by reading a second predetermined number of data bytes from a predetermined location of a payload of another particular frame of said second digital signal; f. checking a payload in a frame of said first digital signal which is delayed by said obtained frame count relative to said frame of said second digital signal from which said data pattern was obtained in step (e) for a match, to said data pattern obtained in step (e), only at said predetermined location from which said data bytes were read in step (e); g. if a match is not found in step (f), going back to step (a), and repeating steps (a) through (g); h. if a match is found in step (f), repeating steps (e) through (g) a predetermined number of times; and i. supplying as an output said frame count as a frame delay indication in units of frames.

Claim 6

The method as defined in claim 3 wherein said step of determining includes the steps of counting a number of bits from a start of frame indication of said second signal until an immediately following start of frame indication of said first signal and supplying as an output said number as a frame offset indication in units of bits.

Claim 7

The method as defined in claim 3 wherein said step of determining includes the steps of converting a frame delay indication from an indication in units of frames to an indication in units of bits and adding said frame delay indication in units of bits to a frame offset indication in units of bits to obtain said difference in delay.

Claim 8

The method as defined in claim 1 wherein said step of aligning said starting location includes the steps of: j. generating third and fourth digital signals each comprising a series of frames of identical type as said frames comprising said first or second digital signals, wherein said third digital signal is transporting a third series of payloads identical to those transported by said first digital signal and said fourth digital signal is transporting a third series of payloads identical to those transported by said second digital signal, and said third and fourth digital signals being time synchronized; k. reading from frames of each of said third and fourth digital signals a pointer value indicating a starting location within respective ones of said frames of a particular payload which is identical in each of said third and fourth series of payloads; l. performing pointer justifications on said fourth digital signal by shifting said starting location and subsequent locations of each payload in said fourth digital signal by an amount reflective of the difference between each of said pointer values read in step (k); m. obtaining a new pointer value for said fourth digital signal so that said new pointer value corresponds with said shifted starting location; n. rechecking said pointer values of said third and fourth digital signals; o. if said pointer values have change going back to step (k) and repeating steps (k) through (o); and v. if said pointer values remain unchanged writing said new pointer value to said fourth digital signal.

Claim 9

The method as defined in claim 7 further including the steps of: writing overhead bytes as required to each of said third and fourth digital signals; scrambling, as required, each of said third and fourth digital signals; and supplying as outputs said third and fourth signals to a signal selector.

Claim 10

The method as defined in claim 1 further including the steps of dividing said first digital signal using a byte disinterleaving technique into a first plurality of signals and dividing second digital signal using said byte disinterleaving technique into a second of plurality of signals, a step of errorlessly switching in a synchronized manner corresponding ones of said first and second plurality of signals thereby supplying a third plurality of signals and a step of combining said third plurality of signals into a third signal using an inverse of said byte disinterleaving technique.

Claim 11

Apparatus in a receiver for errorless switching from a first digital signal comprising a first series of frames in which a first series of payloads is being transported in a first channel, to a second digital signal comprising a second series of frames in which a second series of payloads identical to said first series of payloads is being transported in a second channel, said second series of frames having starting locations, for particular ones of said second series of payloads, that can be different from starting locations of identical particular payloads, in said first series of frames, comprising: means for providing a first delay on said first channel such that said first channel has a total delay including said first delay greater than an actual delay of said second channel; means for aligning each frame of said first digital signal to a corresponding frame of said second digital signal such that each of said corresponding frames has a starting location for an identical particular payload from each of said first and second series of payloads; means responsive to said aligned frames for aligning said starting location and any subsequent locations of particular ones of said second series of payloads within said second series of frames to the starting location and any subsequent locations of identical particular ones of said first series of payloads within said first series of frames; means for determining to switch from said first digital signal to said second digital signal; and means for switching, from said first digital signal to said second digital signal without loss of a single bit, responsive to said means for determining to switch.

Claim 12

Apparatus in a receiver for errorless switching from a first digital signal comprising a first series of frames in which a first series of payloads is being transported in a first channel, to a second digital signal comprising a second series of frames in which a second series of payloads identical to said first series of payloads is being transported in a second channel, said second series of frames having starting locations, for particular ones of said second series of payloads, that can be different from starting locations of identical particular payloads, in said first series of frames, comprising: means for providing a first delay on said first channel such that said first channel has a total delay including said first delay greater than an actual delay of said second channel; means for aligning each frame of said first digital signal to a corresponding frame of said second digital signal such that each of said corresponding frames has a starting location for an identical particular payload from each of said first and second series of payloads; means responsive to said aligned frames for aligning said starting location and any subsequent locations of particular ones of said second series of payloads within said second series of frames to the starting location and any subsequent locations of identical particular ones of said first series of payloads within said first series of frames; means for determining to switch from said first digital signal to said second digital signal; and means for switching, from said first digital signal to said second digital signal without loss of a single bit, responsive to said means for determining to switch.

Claim 13

The apparatus as defined in claim 10 wherein said means for aligning each frame includes: means for measuring the difference in delay between frames of said first digital signal and corresponding frames of said second digital signal; and means for adding a delay to said second channel equal to said measured difference in delay.

Claim 14

The apparatus as defined in claim 11 wherein said means for measuring includes means for determining to within a predetermined probability which frame of said first digital signal corresponds with a frame of said second digital signal.

Claim 15

The apparatus as defined in claim 12 wherein said means for determining to within a predetermined probability includes: means for obtaining a data pattern by reading a first predetermined number of data bytes from a predetermined location of a payload of a particular frame of said second digital signal; means for checking each payload of each successive frame of said first digital signal only at an identical predetermined location as was read by said means for obtaining a data pattern and counting each frame having a payload that is checked until a match to said data pattern is found or until a predetermined duration has passed; means for supplying as an output a frame count indicating the number of frames of said first digital signal that were counted by said means for checking and counting until a match was found; means for restarting and reinitializing said means for checking and counting if a predetermined duration has passed; means for obtaining data patterns repeatedly for a predetermined number of times by reading a second predetermined number of data bytes from a predetermined location of each payload of predetermined particular frames of said second digital signal; means for repeatedly checking for said predetermined number of times a frame in said first digital signal which is delayed by said obtained frame count behind a corresponding frame in said second digital signal from which said data pattern was obtained, said checking being performed only at identical predetermined locations as were read by said means for obtaining data patterns repeatedly for a match to said data patterns and supplying as an output a match indication; means responsive to said match indication for restarting and reinitalizing said means for obtaining, said means for checking and counting, said means for supplying, said means for obtaining, repeatedly and said means for repeatedly checking; and means for supplying as an output said frame count as a frame delay indication in units of frames.

Claim 16

The apparatus as defined in claim 12 wherein said means for determining to within a predetermined probability includes means for counting a number of bits from a start of frame indication of said second digital signal until an immediately following start of frame indication of said first digital signal and supplying as an output said number as a frame offset indication in units of bits.

Claim 17

The apparatus as defined in claim 12 wherein said means for determining to within a predetermined probability includes means for converting a frame delay indication from an indication in units of frames to an indication in units of bits and means for adding said frame delay indication in units of bits to a frame offset indication in units of bits to obtain said difference in delay.

Claim 18

The apparatus as defined in claim 10 wherein said means for aligning said starting location includes: means for generating third and fourth digital signals each comprising a series of frames of identical type as said frames comprising said first or second digital signals, wherein said third digital signal is transporting a series of payloads identical to those transported by said first digital signal and said fourth digital signal is transporting a series of payloads identical to those transported by said second digital signal, and said third and fourth digital signals being time synchronized; means for reading from frames of each of said third and fourth digital signals a pointer value indicating a starting location within respective ones of said frames of a particular payload which is identical in each of said third and fourth series of payloads; means for performing pointer justifications on said fourth digital signal by shifting said starting location and subsequent locations of each payload in said fourth digital signal by an amount reflective of the difference between each of said read pointer values; means for obtaining a new pointer value for said fourth digital signal so that said new pointer value corresponds with said shifted starting location; means for checking said pointer values of said third and fourth digital signals for a change and for supplying as an output a change indication of whether or not a change in said pointer values of said third and fourth digital signals has occurred; means responsive to said change indication indicating that a change has occurred for restarting said means for reading and said means for performing; and means responsive to said change indication indicating that a change has not occurred for writing said new pointer value to said fourth digital signal.

Claim 19

The apparatus as defined in claim 16 further including: means for writing overhead bytes as required to each of said third and fourth digital signals; means for scrambling, as required, each of said third and fourth digital signals; and means for supplying as outputs said third and fourth digital signals to a signal selector for switching.

Claim 20

A system including a plurality of errorless switching apparatus as defined in claim 10 further including means for dividing said first digital signal using a byte disinterleaving technique into a first plurality of signals and means for dividing said second digital signal using said byte disinterleaving technique into a second plurality of signals wherein each of corresponding ones of said first and second plurality of signals are supplied to one of said errorless switching apparatus which operate in a synchronized manner and means for combining each of said signals supplied as an output from each of said plurality of errorless switching apparatus into a third signal using an inverse of said byte disinterleaving technique.