US5049752A — Scanning circuit

Claim 1

Independent Claim 169 words

A scanning circuit for improving the signal-to-noise ration of signals output from detector elements in an infrared detector array to external circuitry during a scan cycle, the scan cycle including a charge accumulation interval and an output interval, the length of the scan cycle determining the frame scan rate, the scanning circuit comprising: (a) a plurality of first circuits connected to dedicated detector elements for accumulating charges representative of the outputs of the detector elements, the charges being accumulated over a charge accumulation interval greater than the output interval; and (b) a plurality of dedicated second circuits connected to said first circuits for outputting signals representative of the accumulated charges to the external circuitry, the signals being output in the output interval, both the charge accumulation interval and the output interval occurring within a single scan cycle; and (c) wherein the effects of transient noise are reduced and a more complete representation of objects within the detector elements field of view is obtained without decreasing the frame scan rate.

Claim 2

Dependent Claim 169 words

A scanning circuit for improving the signal-to-noise ration of signals output from detector elements in an infrared detector array to external circuitry during a scan cycle, the scan cycle including a charge accumulation interval and an output interval, the length of the scan cycle determining the frame scan rate, the scanning circuit comprising: (a) a plurality of first circuits connected to dedicated detector elements for accumulating charges representative of the outputs of the detector elements, the charges being accumulated over a charge accumulation interval greater than the output interval; and (b) a plurality of dedicated second circuits connected to said first circuits for outputting signals representative of the accumulated charges to the external circuitry, the signals being output in the output interval, both the charge accumulation interval and the output interval occurring within a single scan cycle; and (c) wherein the effects of transient noise are reduced and a more complete representation of objects within the detector elements field of view is obtained without decreasing the frame scan rate.

Claim 3

Dependent Claim 22 words

The scanning circuit as recited in claim 1 wherein the charge integration interval is greater than one half of the scan cycle.

Claim 4

Dependent Claim 53 words

The scanning circuit as recited in claim 1 wherein the plurality of first circuits for accumulating charges representative of the outputs of the detector elements accumulate a sufficient portion of the detector's output to improve the probability of detecting changes in the detector output level while maintaining the detector array frame scan rate.

Claim 5

Dependent Claim 79 words

The scanning circuit as recited in claim 1 further comprising: (a) a common output bus for communicating signals from said first circuits to the external circuitry; (b) wherein said second circuits for outputting signals representative of the accumulated charges comprise first switches for communicating the signals representative of the accumulated charges to said common output bus, such that the signals representative of the accumulated charges stored within said first circuits can be sequentially switched to said common output bus.

Claim 6

Dependent Claim 33 words

The scanning circuit as recited in claim 4 wherein said first circuits further comprise first capacitors onto which the accumulated charges representative of the outputs of the detector elements are accumulated and stored.

Claim 7

Dependent Claim 45 words

The scanning circuit as recited in claim 5 wherein said first circuits further comprise second switches for discharging said first capacitors prior to the accumulation of charges thereupon to insure that the charge accumulated upon said capacitors is substantially free from any previously accumulated charge.

Claim 8

Dependent Claim 67 words

The scanning circuit as recited in claim 6 wherein said first circuits further comprise: (a) second capacitors for accumulating charges representative of the output of the detector elements such that the charges are divided among said first and said second capacitors to vary the gain and dynamic range of the first circuits; and (b) third switches for connecting said second capacitors in parallel with said first capacitors.

Claim 9

Dependent Claim 176 words

A scanning circuit for improving the signal-to-noise ratio of signals output from detector elements in an infrared detector array to external circuitry during a scan cycle, the scan cycle including a charge accumulation interval and an output interval, the length of the scan cycle determining the frame scan rate, the scanning circuit comprising: (a) a plurality of charge integrators for receiving the current outputs of dedicated detector elements and integrating the current outputs over a charge accumulation interval; (b) wherein said charge integrators are operative to generate voltage outputs representative of the total current received from the detector elements during the charge accumulation interval; (c) first switches connected to the outputs of said charge integrators for sequentially outputting the voltage output of said charge integrators such that the voltage outputs of said charge integrators can be output in an output interval; and (d) wherein the charge accumulation interval is longer than the output interval and both the charge accumulation interval and the output interval occur within a single scan cycle without decreasing the frame scan rate.

Claim 10

Dependent Claim 176 words

A scanning circuit for improving the signal-to-noise ratio of signals output from detector elements in an infrared detector array to external circuitry during a scan cycle, the scan cycle including a charge accumulation interval and an output interval, the length of the scan cycle determining the frame scan rate, the scanning circuit comprising: (a) a plurality of charge integrators for receiving the current outputs of dedicated detector elements and integrating the current outputs over a charge accumulation interval; (b) wherein said charge integrators are operative to generate voltage outputs representative of the total current received from the detector elements during the charge accumulation interval; (c) first switches connected to the outputs of said charge integrators for sequentially outputting the voltage output of said charge integrators such that the voltage outputs of said charge integrators can be output in an output interval; and (d) wherein the charge accumulation interval is longer than the output interval and both the charge accumulation interval and the output interval occur within a single scan cycle without decreasing the frame scan rate.

Claim 11

Dependent Claim 83 words

The scanning circuit as recited in claim 8 wherein said charge integrators comprise: (a) first capacitors for storing the output of the dedicated detector elements to which said charge integrators are connected, the output of the detector element being stored as a charge, the voltage across said first capacitors being representative of the amount of output so stored; and (b) second switches for discharging said first capacitors prior to each interrogation of the dedicated detector elements to which said charge integrators are connected.

Claim 12

Dependent Claim 125 words

The scanning circuit as recited in claim 9 wherein each of said charge integrators further comprises: (a) at least one second capacitor, said second capacitor being connectable in parallel with said first capacitor, the current output of the detector element being split between said first and second capacitors such that the gain of said charge integrator is reduced and the dynamic range of said charge integrator is increased when said second capacitor is connected in parallel with said first capacitor; and (b) third switches for connecting said second capacitor in parallel with said first capacitor; (c) wherein said second switches discharge said second capacitors as well as said first capacitors prior to each interrogation of the detector elements to which the charge integrators are connected.

Claim 13

Dependent Claim 43 words

The scanning circuit as recited in claim 10 further comprising high pass filters connected intermediate said charge integrators and said first switches to reduce constant background information content of the detector element signal to reduce the amount of processing required by external circuitry.

Claim 14

Dependent Claim 38 words

The scanning circuit as recited in claim 11 wherein the charge integrators further function as low pass filters to remove high frequency noise from the detector output signals to reduce the amount of processing required by external circuitry.

Claim 15

Independent Claim 165 words

A method for processing output signals from detector elements in an infrared detector array during a scan cycle, the scan cycle including a charge accumulation interval and an output interval, the length of the scan cycle determining the frame scan rate, to increase the signal to noise ration characteristics of the output signals the method comprising: (a) accumulating charges representative of the outputs of the detector elements, the charges being accumulated over the charge accumulation interval; and (b) outputting signals representative of the accumulated charges to external circuitry, the signals being output over the output interval, both the charge accumulation interval and the output interval occurring within a single scan cycle; (c) wherein the charge accumulation interval is greater than the output interval such that the effects of transient noise are reduced and a more complete representation of objects within the detector element field of view can be obtained without the detector element field of view can be obtained without decreasing the frame scan rate.

Claim 16

Independent Claim 165 words

A method for processing output signals from detector elements in an infrared detector array during a scan cycle, the scan cycle including a charge accumulation interval and an output interval, the length of the scan cycle determining the frame scan rate, to increase the signal to noise ration characteristics of the output signals the method comprising: (a) accumulating charges representative of the outputs of the detector elements, the charges being accumulated over the charge accumulation interval; and (b) outputting signals representative of the accumulated charges to external circuitry, the signals being output over the output interval, both the charge accumulation interval and the output interval occurring within a single scan cycle; (c) wherein the charge accumulation interval is greater than the output interval such that the effects of transient noise are reduced and a more complete representation of objects within the detector element field of view can be obtained without the detector element field of view can be obtained without decreasing the frame scan rate.

Claim 17

Dependent Claim 55 words

The method as recited in claim 13 wherein the step of accumulating charges representative of the outputs of the detector elements over a charge accumulation interval comprises capturing a sufficient portion of the detector's output to improve the probability of detecting changes in the detector output level while maintaining the detector array frame scan rate.

Claim 18

Dependent Claim 33 words

The method as recited in claim 13 wherein the step of outputting signals representative of the accumulated charges comprises sequentially switching the signals representative of the accumulated charges to a common output bus.

Claim 19

Dependent Claim 99 words

The method as recited in claim 15 wherein: (a) the step of accumulating charges representative of the outputs of detector elements further comprises accumulating and storing the charges representative of the outputs of detector elements upon capacitors; and (b) the step of outputting signals representative of the accumulated charges further comprises multiplexing the signals representative of the accumulated charges to a common output bus in response to externally generated address signals, the externally generated address signals being sequentially applied to switches to enable the switches to output the signals representative of the accumulated charges to the common output bus.

Claim 20

Dependent Claim 48 words

The method as recited in claim 16 further comprising the step of discharging the capacitors prior to the step of accumulating charges representative of the outputs of detector elements upon the capacitors, to insure that the charges accumulated upon the capacitors are free from any previously accumulated charge.

Claim 21

Dependent Claim 102 words

The method as recited in claim 17 wherein: (a) the step of accumulating charges representative of the outputs of the detector elements comprises accumulating the charges upon a plurality of capacitors such that the charge representative of the output of a particular detector element can be divided among more than one capacitor to vary the gain and dynamic range of the circuit; and (b) the step of discharging the capacitors prior to the step of accumulating charges representative of the outputs of detector elements further comprises discharging all capacitors upon which charges representative of the outputs of the detector elements are stored.

Claim 22

Dependent Claim 37 words

The method as recited in claim 18 wherein the step of accumulating charges representative of the outputs of detector elements and the step of outputting signals representative of the accumulated charges occur within a single scan cycle.

Claim 23

Dependent Claim 53 words

The method as recited in claim 18 wherein the step of outputting signals representative of the accumulated charges is delayed with respect to the step of accumulating charges representative of the outputs of detector elements such that the step of outputting signals representative of the accumulated charges occurs outside a single scan cycle.

Claim 24

Independent Claim 193 words

A method for improving the signal to noise ratio of the output of detector elements in an infrared detector array during a scan cycle, the scan cycle including a charge accumulation interval and an output interval, the length of the scan cycle determining the frame scan rate, the method comprising: (a) communicating the output of a plurality of detector elements to a corresponding plurality of dedicated charge integrators over the charge accumulation interval; (b) generating voltages at the output of the charge integrators, the voltages being representative of the total output from the detector elements to their dedicated charge integrators; (c) sequentially connecting the voltages formed within the charge integrators to a common output bus, such that the voltages formed by all charge integrators are connected to the common output bus within the output interval; (d) wherein the charge accumulation interval is greater than the output interval and both the charge accumulation interval and the output interval occur within a single scan cycle without decreasing the frame scan rate; and (e) wherein the signal-to-noise ratio of the output of the detector elements is increased by increasing the interrogation time of the detector elements.

Claim 25

Independent Claim 193 words

A method for improving the signal to noise ratio of the output of detector elements in an infrared detector array during a scan cycle, the scan cycle including a charge accumulation interval and an output interval, the length of the scan cycle determining the frame scan rate, the method comprising: (a) communicating the output of a plurality of detector elements to a corresponding plurality of dedicated charge integrators over the charge accumulation interval; (b) generating voltages at the output of the charge integrators, the voltages being representative of the total output from the detector elements to their dedicated charge integrators; (c) sequentially connecting the voltages formed within the charge integrators to a common output bus, such that the voltages formed by all charge integrators are connected to the common output bus within the output interval; (d) wherein the charge accumulation interval is greater than the output interval and both the charge accumulation interval and the output interval occur within a single scan cycle without decreasing the frame scan rate; and (e) wherein the signal-to-noise ratio of the output of the detector elements is increased by increasing the interrogation time of the detector elements.

Claim 26

Dependent Claim 65 words

The method as recited in claim 21 wherein the step of communicating the output of a plurality of detector elements to a corresponding plurality of dedicated charge integrators comprises: (a) discharging a plurality of first capacitors to insure that substantially none of any charge previously accumulated thereon remains; and (b) communicating the output of a plurality of detector elements to the plurality of first capacitors.

Claim 27

Dependent Claim 100 words

The method as recited in claim 22 wherein the step of communicating the output of a plurality of detector elements to a corresponding plurality of dedicated charge integrators further comprises: (a) discharging a plurality of second capacitors when discharging the plurality of first capacitors to insure that substantially none of any charge previously accumulated upon the second capacitors remains; and (b) simultaneously communicating the outputs of the plurality of detector elements to the plurality of second capacitors when the current outputs are communicated to the plurality of first capacitors, to vary the gain and dynamic range of the charge integrator.

Claim 28

Dependent Claim 40 words

The method as recited in claim 23 further comprising the step of filtering low frequency components out of the detector signals prior to the step of sequentially connecting the voltage formed within each charge integrator to a common output bus.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1994-09-16	1995-03-18	1995-09-17	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1998-09-16	1999-03-18	1999-09-17	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2002-09-16	2003-03-18	2003-09-17	$7700.00	Window Closed / Lapsed

Scanning circuit

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