US5048062A — Transmitting commands over a serial link

Claim 1

Independent Claim 95 words

Apparatus for generating commands in a system wherein multi-bit characters are continuously sent from a sender to a receiver to acquire character synchronization, said apparatus comprising: register means for providing a multi-bit idle character; bit modifying means connected to said register means for changing selected bits of said multi-bit idle character for forming a command character which is a modification of said multi-bit idle character; and multiplexing means for forming an ordered set of characters, said ordered set having said multi-bit idle character as a first character and said command character as a second character.

Claim 2

Dependent Claim 95 words

Apparatus for generating commands in a system wherein multi-bit characters are continuously sent from a sender to a receiver to acquire character synchronization, said apparatus comprising: register means for providing a multi-bit idle character; bit modifying means connected to said register means for changing selected bits of said multi-bit idle character for forming a command character which is a modification of said multi-bit idle character; and multiplexing means for forming an ordered set of characters, said ordered set having said multi-bit idle character as a first character and said command character as a second character.

Claim 3

Dependent Claim 57 words

The apparatus of claim 1 wherein said register means is a latch in which the bits of each successive multi-bit idle character are inverted from the previously provided multi-bit idle character such that said first character of said ordered set has a first disparity and said second character of said ordered set has a second, opposite disparity.

Claim 4

Dependent Claim 34 words

The apparatus of claim 2 wherein said first character of said ordered set is a K28.5 + idle character and said second character of said ordered set is a modified K28.5 - idle character.

Claim 5

Independent Claim 100 words

An apparatus for receiving synchronizing multi-bit characters, said apparatus comprising: a recognition circuit having an input for receiving an ordered set and an output for providing a FUNCTION OUT message, said recognition circuit having detection means for detecting a first idle character in said received ordered set and latch means for providing said FUNCTION OUT message responsive to a second character in said received ordered set; a first detector in said detection means for detecting an idle character having a first disparity; and a second detector in said detection means for detecting an idle character having a second, opposite disparity.

Claim 6

Independent Claim 100 words

An apparatus for receiving synchronizing multi-bit characters, said apparatus comprising: a recognition circuit having an input for receiving an ordered set and an output for providing a FUNCTION OUT message, said recognition circuit having detection means for detecting a first idle character in said received ordered set and latch means for providing said FUNCTION OUT message responsive to a second character in said received ordered set; a first detector in said detection means for detecting an idle character having a first disparity; and a second detector in said detection means for detecting an idle character having a second, opposite disparity.

Claim 7

Dependent Claim 55 words

The apparatus of claim 4 further comprising: sequence generating means having an input and an output, said sequence generating means generating ordered sets of characters on its output wherein the first character of each ordered set is an idle character and the second character of each ordered set is a modification of said idle character.

Claim 8

Dependent Claim 25 words

The apparatus of claim 5 wherein said first detector detects a K28.5 + idle character and said second detector detects a K28.5 - idle character.

Claim 9

Dependent Claim 63 words

The apparatus of claim 5 wherein said first detector and said second detector have outputs, and said recognition circuit further comprises a synchronization means connected to the outputs of said first and second detectors, said synchronization means for synchronizing said first and second detectors until one of said first or second detectors detects a first idle character of one of said ordered sets.

Claim 10

Dependent Claim 45 words

The apparatus of claim 7 wherein said recognition circuit further comprises a state machine connected to the outputs of said first and second detectors, said state machine having an error state representative of two idle characters having the same disparity being detected in a row.

Claim 11

Dependent Claim 26 words

The apparatus of claim 8 wherein said latch means latches selected ones of the most significant bits of said second character as said FUNCTION OUT message.

Claim 12

Dependent Claim 47 words

The apparatus of claim 9 wherein said detection means further comprises a third detector for detecting a selected sub-block of least significant bits of said second character, said selected sub-block of least significant bits being selected to be invariant in selected available characters of said second character.

Claim 13

Dependent Claim 82 words

The apparatus of claim 10 wherein said third detector has an output connected to said state machine, said state machine having an idle detect state representative of an idle character being detected by said detection means, and a FUNCTION OUT state representative of said sub-block being detected by said third detector, said state machine only allowing state moves to said FUNCTION OUT state from said idle detect state such that FUNCTION OUT messages are provided upon the detection of said ordered sets.

Claim 14

Independent Claim 141 words

A method of selecting a second character of an ordered set wherein the first character of said ordered set is an idle character and the second characters is a command character, said method comprising the steps of: a. establishing said idle character as a base character; b. arranging all valid 8B/10B data characters in sequence such that the first 8B/10B data character has the maximum number of its least significant bits in the same pattern as the base character and the last 8B/10B data character in the sequence has none of its least significant bits in the same pattern as the base character; and c. selecting the number of 8B/10B data characters in the sequence as the number of command characters desired such that the maximum number of least significant bits of the command characters are invarient from the base character.

Claim 15

Independent Claim 141 words

A method of selecting a second character of an ordered set wherein the first character of said ordered set is an idle character and the second characters is a command character, said method comprising the steps of: a. establishing said idle character as a base character; b. arranging all valid 8B/10B data characters in sequence such that the first 8B/10B data character has the maximum number of its least significant bits in the same pattern as the base character and the last 8B/10B data character in the sequence has none of its least significant bits in the same pattern as the base character; and c. selecting the number of 8B/10B data characters in the sequence as the number of command characters desired such that the maximum number of least significant bits of the command characters are invarient from the base character.

Claim 16

Dependent Claim 142 words

A data transmission apparatus synchronized by the continuous transmission of multi-bit characters, said data transmission apparatus comprising: a switch having at least two ports; and a switch controller for controlling switching between said ports by said switch; each of said ports including an input for receiving data characters transmitted to said port and an output for sending data characters transmitted from said port; each of said ports further including a recognition circuit having an input for receiving an ordered set of said multi-bit characters from its attached link and an output connected to said switch controller for providing to said switch controller a FUNCTION OUT message, said recognition circuit having detection means for detecting a first idle character in said received ordered set, and latch means for providing said FUNCTION OUT message responsive to a second character in said received ordered set.

Claim 17

Dependent Claim 142 words

A data transmission apparatus synchronized by the continuous transmission of multi-bit characters, said data transmission apparatus comprising: a switch having at least two ports; and a switch controller for controlling switching between said ports by said switch; each of said ports including an input for receiving data characters transmitted to said port and an output for sending data characters transmitted from said port; each of said ports further including a recognition circuit having an input for receiving an ordered set of said multi-bit characters from its attached link and an output connected to said switch controller for providing to said switch controller a FUNCTION OUT message, said recognition circuit having detection means for detecting a first idle character in said received ordered set, and latch means for providing said FUNCTION OUT message responsive to a second character in said received ordered set.

Claim 18

Dependent Claim 38 words

The data transmission system of claim 13 wherein said detection means comprises a first detector for detecting an idle character having a first disparity, and a second detector for detecting an idle character having a second, opposite disparity.

Claim 19

Dependent Claim 27 words

The data transmission apparatus of claim 14 wherein said first detector detects a K28.5 + idle character and said second detector detects a K28.5 - idle character.

Claim 20

Dependent Claim 65 words

The data transmission apparatus of claim 15 wherein said first detector and said second detector have outputs, and said recognition circuit further comprises a synchronization means connected to the outputs of said first and second detectors, said synchronization means for synchronizing said first and second detectors until one of said first or second detectors detects a first idle character of one of said ordered sets.

Claim 21

Dependent Claim 47 words

The data transmission apparatus of claim 16 wherein said recognition circuit further comprises a state machine connected to the outputs of said first and second detectors, said state machine having an error state representative of two idle characters having the same disparity being detected in a row.

Claim 22

Dependent Claim 28 words

The data transmission apparatus of claim 17 wherein said latch means latches selected ones of the most significant bits of said second character as said FUNCTION OUT message.

Claim 23

Dependent Claim 49 words

The data transmission apparatus of claim 18 wherein said detection means further comprises a third detector for detecting a selected sub-block of least significant bits of said second character, said selected sub-block of least significant bits being selected to be invariant in selected available characters of said second character.

Claim 24

Dependent Claim 84 words

The data transmission apparatus of claim 19 wherein said third detector has an output connected to said state machine, said state machine having an idle detect state representative of an idle character being detected by said detection means, and a FUNCTION OUT state representative of said sub-block being detected by said third detector, said state machine only allowing state moves to said FUNCTION OUT state from said idle detect state such that FUNCTION OUT messages are provided upon the detection of said ordered sets.

Claim 25

Dependent Claim 57 words

The data transmission apparatus of claim 20 further comprising: sequence generating means having an input and an output, said sequence generating means generating ordered sets of characters on its output wherein the first character of each ordered set is an idle character and the second character of each ordered set is a modification of said idle character.

Claim 26

Dependent Claim 83 words

The data transmission apparatus of claim 13 further comprising: a link attached to each port, each of said links having two data transmission conductors, one data transmission conductor connected to the input of the attached port for transmitting data to the attached port and the other data transmission conductor connected to the output of the attached port for transmitting data from the attached port; and a link-level facility attached to each link for sending data to and receiving data from the attached port.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1994-09-09	1995-03-11	1995-09-10	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1998-09-09	1999-03-11	1999-09-10	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2002-09-09	2003-03-11	2003-09-10	$7700.00	Window Closed / Lapsed

Transmitting commands over a serial link

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