Neural network

Claim 2

A neural network comprising: a plurality of synapse circuits, each synapse circuit having an input, an output and adjustable coupling means for changing the degree of electrical coupling between the input and output; a plurality of signal input terminals respectively connected to inputs of said synapse circuits for supplying logic signals to respective synapse circuits; signal conversion means commonly connected to the outputs of said synapse circuits for integrating collective analog output signals of said synapse circuits and, with reference to a predetermined threshold, generating an associated binary signal; control signal generating means for generating coupling control signals in response to an error between an externally applied reference educator signal and said binary signal, said control signal generating means comprising first logic means for reducing the degree of coupling of said synapse circuits when said error is of positive polarity and second logic means for increasing the degree of coupling of said synapse circuits when said error is of negative polarity; and a plurality of gate means individually provided between the adjustable coupling means of each synapse circuit and said control signal generating means for applying said coupling control signals to said adjustable coupling means in response to corresponding logic signals applied to the input terminals of the synapse circuits.

Claim 3

A neural network in accordance with claim 1, wherein said adjustable coupling means comprises means to change the synapse circuit output voltage in response to said coupling control signal when a logic signal applied to said signal input terminal is in a first logic state.

Claim 4

A neural network in accordance with claim 1, wherein said adjustable coupling means comprises: a plurality of transistors for varying impedance, being connected in parallel with each other and having first ends connected to an output of said synapse circuit, a power supply for introducing a reference voltage, switching means interposed between respective second ends of said plurality of transistors and said power supply line to perform on-off operation in response to a logic signal applied to the corresponding signal input terminal, and counter means performing a counting operation in response to a control signal received from a corresponding one of said plurality of gate means for selectively causing conduction of said transistors for varying coupling impedance of the synapse circuit.

Claim 5

A neural network in accordance with claim 3, wherein said power supply is provided with a first power supply line for introducing a first reference voltage for a stimulative signal and a second power supply line for introducing a second reference voltage for an inhibitory signal, said plurality of transistors for varying coupling impedance and said switching means being responsively provided in pairs respectively.

Claim 6

A neural network in accordance with claim 3, wherein said counter means includes: a shift register having unit registers of the same number as said transistors for varying impedance, and a control circuit for controlling a shifting operation of said shift register in response to said control signal.

Claim 7

A neural network in accordance with claim 5, wherein said control circuit controls the number of logic data introduced into said shift register and shifting operation thereof.

Claim 8

A neural network in accordance with claim 1, wherein said signal conversion means comprises a threshold amplifier.

Claim 9

A neural network in accordance with claim 1, wherein said control signal generating means generates two control signals, to express three states representing an increase coupling command, a decrease coupling command and a maintain coupling command for setting said degree of electrical coupling of said synapse circuits by logic combinations of said two control signals.

Claim 10

A neural network in accordance with claim 1, wherein said plurality of said synapse circuits and said plurality of said gate means are provided in a matrix array with respective rows connected to said signal input terminals, and wherein respective columns of said matrix array are connected to a plurality of said signal conversion means, a plurality of said educator signal input means and a plurality of said control signal generating means.

Claim 11

A neural network in accordance with claim 1, wherein each said synapse circuit includes a non-volatile semiconductor memory device.

Claim 12

A multiple neural network comprising: a plurality of signal input terminals for inputting a plurality of logic signals; a first neural circuit receiving said plurality of logic signals from said plurality of signal input terminals for outputting a plurality of intermediate stage signals, said first neural circuit comprising: (a) a first synapse array comprising a plurality of synapse circuits, each synapse circuit having an input, an output and adjustable coupling means for changing the degree of electrical coupling between the input and output, and (b) a plurality of first signal conversion means connected to respective columns of said first synapse array for integrating collective analog output signals of said synapse circuits connected thereto and, with reference to a predetermined threshold, generating intermediate stage binary signals; and a second neural circuit receiving said plurality of intermediate stage signals outputted from said first neural circuit as input signals, for outputting at least one associated corresponding signal, said second neural circuit comprising: (c) a plurality of second synapse circuits for receiving respective outputs from said plurality of first signal conversion means, each of said second synapse circuits having an input, an output and adjustable coupling means for changing the degree of electrical coupling between the input and output, and (d) second signal conversion means commonly connected to respective outputs of said second synapse circuits for integrating collective analog output signals of said second synapse circuits connected thereto and, with reference to a predetermined threshold, generating associated binary signals; first learning means for adjusting the degree of electrical coupling of said first neural circuit; and second learning means for adjusting the degree of electrical coupling of said second neural circuit.

Claim 13

A multiple neural network comprising: a plurality of signal input terminals for inputting a plurality of logic signals; a first neural circuit receiving said plurality of logic signals from said plurality of signal input terminals for outputting a plurality of intermediate stage signals, said first neural circuit comprising: (a) a first synapse array comprising a plurality of synapse circuits, each synapse circuit having an input, an output and adjustable coupling means for changing the degree of electrical coupling between the input and output, and (b) a plurality of first signal conversion means connected to respective columns of said first synapse array for integrating collective analog output signals of said synapse circuits connected thereto and, with reference to a predetermined threshold, generating intermediate stage binary signals; and a second neural circuit receiving said plurality of intermediate stage signals outputted from said first neural circuit as input signals, for outputting at least one associated corresponding signal, said second neural circuit comprising: (c) a plurality of second synapse circuits for receiving respective outputs from said plurality of first signal conversion means, each of said second synapse circuits having an input, an output and adjustable coupling means for changing the degree of electrical coupling between the input and output, and (d) second signal conversion means commonly connected to respective outputs of said second synapse circuits for integrating collective analog output signals of said second synapse circuits connected thereto and, with reference to a predetermined threshold, generating associated binary signals; first learning means for adjusting the degree of electrical coupling of said first neural circuit; and second learning means for adjusting the degree of electrical coupling of said second neural circuit.

Claim 14

A neural network in accordance with claim 11, wherein said second neural circuit comprises: (a) a second array of synapse circuits, each synapse circuit of said second array including input terminals coupled to receive said first control signal and output terminals and a plurality of variable connector elements for changing the degree of electrical coupling between an input terminal and an output terminal, and (b) a plurality of second gate means connected to corresponding ones of said first synapse circuits for performing switching operation in response to logic signals at said signal input terminals; and said first learning means comprises: a plurality of second control signal generating means for generating a second control signal for controlling increase, decrease and maintenance of degrees of electrical coupling of said first synapse circuits in corresponding columns on the basis of analog output signals from corresponding ones of said plurality of variable connector elements and said analog output signals from said first neural circuit, said second control signal generating means being connected to corresponding ones of said second gate means.

Claim 15

A neural network in accordance with claim 12, wherein said first control signal generating means generates two control signals and a pair of said variable connector elements in each said second synapse circuit operate in response thereto, and said second control signal generating means includes a differential amplifier for comparing levels of two analog signals from a corresponding pair of said variable connector elements.

Claim 16

A neural network in accordance with claim 13, wherein said first control signal generating means includes: first level detecting means for detecting whether or not the levels of said analog signals input to said second signal conversion means are in a prescribed level range, and gate means for controlling output of said first control signal in response to said first level detecting means, and said second control signal generating means includes: second level detecting means for detecting whether or not the levels of said analog signals input to said first signal conversion means are within a prescribed level range, and gate means for controlling output of said second control signal in response to said second level detecting means.

Claim 17

A neural network in accordance with claim 11, wherein said second learning means includes: means for inputting educator signals for learning; first control signal generating means for generating a first control signal for controlling increase, decrease and maintenance of degrees of electrical coupling of said second synapse circuits on the basis of said associated binary signals, said analog output signals of said first synapse circuits and said educator signals, and a plurality of first gate means individually provided between said second synapse circuits and said first control signal generating means for applying coupling control signals to said second synapse circuits in response to corresponding ones of said intermediate stage binary signals, whereby said second synapse circuits change degrees of electrical coupling between input and output in response to said first control signal supplied through said first gate means.

Claim 18

A neural network in accordance with claim 15, wherein a plurality of said second synapse circuits and a plurality of said first gate means correspond to respective ones of said first signal conversion means, and a plurality of said educator signal input means and a plurality of said first control signal generating means are provided in correspondence thereto.