Storage area structure in information processor

Claim 2

A storage area structure connected to an information processor, said storage area structure comprising: a first storage area allocated on a main memory for storing object information, said object information being instructions for controlling operation of said information processor; a second storage area constituting an address converting table; and a third storage area for storing an address indicating a respective object information stored in the first storage area through the address converting table; wherein said second storage area includes an additional area for storing class information which is a part of said object information stored in the first storage area; and wherein said address stored in said third storage area is used by said information processor to access said first storage area by applying said address to said address converting table of said second storage area which converts said address into an address which is applied to said first storage area and wherein said part class information which is a part of said object information stored in said second storage area is used to determine subsequent operations of said information processor.

Claim 3

A storage area structure in an information processor as set forth in claim 1, wherein said additional area stores information required to determine an operation to be executed by the information processor.

Claim 4

A storage area structure in an information processor as set forth in claim 2, wherein the information is written into the additional area by execution of a micro program.

Claim 5

A storage area structure, connected to an information processor, including a plurality of storage areas, said storage area structure comprising: a first storage area assigned to a main memory, for storing object information including class information indicating a class of said object, said object information being instructions used for controlling the operation of said information processor and said class information being used to determine subsequent operations of said information processor; a second storage area for storing entry information related to a respective object information of said first storage area, said second storage area being arranged to form an address converting table for converting a pointing address to an address of said first storage area; a third storage area for storing said pointing address which points to an address of a particular object information in said first storage area through said address conversion table; wherein said third storage area is used by said information processor to access said first storage area through said second storage area; and wherein said entry information includes an address and said class information for a respective object information such that only said first storage area pointed to by said third storage area through said second storage area need to be accessed by said information processor to determine a subsequent operation of said information processor.

Claim 6

A storage area structure, connected to an information processor, including a plurality of storage areas, said storage area structure comprising: a first storage area assigned to a main memory, for storing object information including class information indicating a class of said object, said object information being instructions used for controlling the operation of said information processor and said class information being used to determine subsequent operations of said information processor; a second storage area for storing entry information related to a respective object information of said first storage area, said second storage area being arranged to form an address converting table for converting a pointing address to an address of said first storage area; a third storage area for storing said pointing address which points to an address of a particular object information in said first storage area through said address conversion table; wherein said third storage area is used by said information processor to access said first storage area through said second storage area; and wherein said entry information includes an address and said class information for a respective object information such that only said first storage area pointed to by said third storage area through said second storage area need to be accessed by said information processor to determine a subsequent operation of said information processor.

Claim 7

A memory area structure connected to a data processor including a plurality of memory areas, said memory area structure comprising: a first memory area for storing instruction information which is used to control the operation of said data processor; a second memory area for storing first address information being used to access said first memory area and for storing a portion of said instruction information; and a third memory area for storing second address information being used to access said second memory area, wherein said third memory area is used by said data processor to access said first memory area through said second memory area and wherein said portion of said instruction stored in said second memory area is used to determine a subsequent operation of said data processor.

Claim 8

A memory area structure connected to a data processor including a plurality of memory areas, said memory area structure comprising: a first memory area for storing instruction information which is used to control the operation of said data processor; a second memory area for storing first address information being used to access said first memory area and for storing a portion of said instruction information; and a third memory area for storing second address information being used to access said second memory area, wherein said third memory area is used by said data processor to access said first memory area through said second memory area and wherein said portion of said instruction stored in said second memory area is used to determine a subsequent operation of said data processor.

Claim 9

A memory area structure according to claim 5, wherein said instruction information includes data and procedure information for controlling said data processor.

Claim 10

A memory area structure connected to a data processor including a plurality of memory areas, said memory area structure comprising: a first memory area for storing instruction information which is used to control the operation of said data processor; a second memory area for storing first address information being used to access said first memory area and for storing a portion of said instruction information; and a third memory area for storing second address information being used to access said second memory area, wherein said third memory area is used by said data processor to access said first memory area through said second memory area and said portion of said instruction stored in said second memory area is used to determine a subsequent operation of said data processor; wherein said instruction information includes data and procedure information for controlling said data processor; and wherein said portion of said instruction information stored in said second memory area includes said procedure information.

Claim 11

A memory area structure connected to a data processor including a plurality of memory areas, said memory area structure comprising: a first memory area for storing instruction information which is used to control the operation of said data processor; a second memory area for storing first address information being used to access said first memory area and for storing a portion of said instruction information; and a third memory area for storing second address information being used to access said second memory area, wherein said third memory area is used by said data processor to access said first memory area through said second memory area and said portion of said instruction stored in said second memory area is used to determine a subsequent operation of said data processor; wherein said instruction information includes data and procedure information for controlling said data processor; and wherein said portion of said instruction information stored in said second memory area includes said procedure information.

Claim 12

A memory area structure according to claim 7, wherein said instruction information is object information which is a unit of a program; and wherein said portion of said instruction information is class information which identifies a class to which said object information belongs, said class information being used to determine a subsequent operation of said data processor.