Semiconductor integrated circuit including an intrinsic MOS transistor for generating a reference voltage

Claim 2

A semiconductor integrated circuit for generating a reference voltage, comprising: a semiconductor substrate; a first voltage terminal connected to a first voltage source; a load element formed in the semiconductor substrate and having two ends, one end of which is connected to the first voltage terminal; a second voltage terminal connected to a second voltage source; an MOS transistor formed in the semiconductor substrate and having a source, a drain, a gate and a channel having no ion-implanted region therein for threshold voltage control; means for connecting the other end of the load element to the source; means for connecting the second voltage terminal to the drain; means for connecting the drain to the gate; and an output terminal connected to the other end of the load element and to the source.

Claim 3

A semiconductor integrated circuit according to claim 1, wherein the impurity concentration of the channel of the MOS transistor is substantially the same as that of the semiconductor substrate.

Claim 4

A semiconductor integrated circuit according to claim 1, wherein the load element comprises a resistor.

Claim 5

A semiconductor integrated circuit according to claim 1, wherein the load element comprises an MOS transistor.

Claim 6

A semiconductor integrated circuit according to claim 1, further comprising: means for connecting the substrate of the MOS transistor to the source.

Claim 7

A semiconductor integrated circuit according to claim 1, further comprising a third voltage terminal connected to the substrate.

Claim 8

A semiconductor integrated circuit according to claim 1, wherein the MOS transistor comprises a P-channel transistor.

Claim 9

A semiconductor integrated circuit according to claim 1, wherein said means for connecting the other end of the load element to the source comprises wiring.

Claim 10

A semiconductor integrated circuit according to claim 1, wherein said means for connecting the other end of the load element to the source comprises a resistor.

Claim 11

A semiconductor integrated circuit according to claim 1, wherein said means for connecting the second voltage terminal to the drain comprises wiring.

Claim 12

A semiconductor integrated circuit according to claim 1, wherein said means for connecting the drain to the gate comprises wiring.

Claim 13

A semiconductor integrated circuit for generating a reference voltage, comprising: a semiconductor substrate having a first conductivity type; a first voltage terminal connected to a first voltage source; a load element formed in the semiconductor substrate and having two ends, one end of which is connected to the first voltage terminal; a second voltage terminal connected to a second voltage source; a well impurity region of a second conductivity type formed in the substrate: an MOS transistor formed in the well impurity region and having a channel with an impurity concentration substantially the same as that of an upper portion of the well impurity region, a source, a drain and a gate; means for connecting the other end of the load element to the source; means for connecting the second voltage terminal to the drain; means for connecting the drain to the gate; and an output terminal connected to the other end of the load element and to the source.

Claim 14

A semiconductor integrated circuit for generating a reference voltage, comprising: a semiconductor substrate having a first conductivity type; a first voltage terminal connected to a first voltage source; a load element formed in the semiconductor substrate and having two ends, one end of which is connected to the first voltage terminal; a second voltage terminal connected to a second voltage source; a well impurity region of a second conductivity type formed in the substrate: an MOS transistor formed in the well impurity region and having a channel with an impurity concentration substantially the same as that of an upper portion of the well impurity region, a source, a drain and a gate; means for connecting the other end of the load element to the source; means for connecting the second voltage terminal to the drain; means for connecting the drain to the gate; and an output terminal connected to the other end of the load element and to the source.

Claim 15

A semiconductor integrated circuit for generating a reference voltage, comprising: a semiconductor substrate having a first conductivity type; a first voltage terminal connected to a first voltage source; a load element formed in the semiconductor substrate and having two ends, one end of which is connected to the first voltage terminal; a second voltage terminal connected to a second voltage source; a first well impurity region of a second conductivity type formed in the substrate; a second well impurity region of the first conductivity type formed in the first well impurity region; an MOS transistor formed in the second well impurity region and having a channel with an impurity concentration substantially the same as that of an upper portion of the second well impurity region, a source, a drain and a gate; means for connecting the other end of the load element to the source; means for connecting the second voltage terminal to the drain; means for connecting the drain to the gate; and an output terminal connected to the other end of the load element and to the source.

Claim 16

A semiconductor integrated circuit for generating a reference voltage, comprising: a semiconductor substrate having a first conductivity type; a first voltage terminal connected to a first voltage source; a load element formed in the semiconductor substrate and having two ends, one end of which is connected to the first voltage terminal; a second voltage terminal connected to a second voltage source; a first well impurity region of a second conductivity type formed in the substrate; a second well impurity region of the first conductivity type formed in the first well impurity region; an MOS transistor formed in the second well impurity region and having a channel with an impurity concentration substantially the same as that of an upper portion of the second well impurity region, a source, a drain and a gate; means for connecting the other end of the load element to the source; means for connecting the second voltage terminal to the drain; means for connecting the drain to the gate; and an output terminal connected to the other end of the load element and to the source.

Claim 17

A semiconductor integrated circuit for generating an internal power source voltage comprising: a semiconductor substrate; a first voltage terminal connected to a first voltage source; a load element formed in the semiconductor substrate and having two ends, one end of which is connected to the first voltage terminal; a second voltage terminal connected to a second voltage source; an MOS transistor formed in the semiconductor substrate and having a source, a drain and a gate and a channel having no ion-implanted region therein for threshold voltage control; means for connecting the other end of the load element to the source; means for connecting the second voltage terminal to the drain; means for connecting the drain to the gate; an output terminal connected to the other end of the load element and to the source; and a power source voltage generating circuit formed in the semiconductor substrate and having a reference voltage level input terminal connected to the output terminal, at least one MOS transistor which is formed with channel ion-implantation, and an internal power source voltage between the voltage level of the output terminal and the voltage level of the second voltage terminal.

Claim 18

A semiconductor integrated circuit for generating an internal power source voltage comprising: a semiconductor substrate; a first voltage terminal connected to a first voltage source; a load element formed in the semiconductor substrate and having two ends, one end of which is connected to the first voltage terminal; a second voltage terminal connected to a second voltage source; an MOS transistor formed in the semiconductor substrate and having a source, a drain and a gate and a channel having no ion-implanted region therein for threshold voltage control; means for connecting the other end of the load element to the source; means for connecting the second voltage terminal to the drain; means for connecting the drain to the gate; an output terminal connected to the other end of the load element and to the source; and a power source voltage generating circuit formed in the semiconductor substrate and having a reference voltage level input terminal connected to the output terminal, at least one MOS transistor which is formed with channel ion-implantation, and an internal power source voltage between the voltage level of the output terminal and the voltage level of the second voltage terminal.

Claim 19

A semiconductor integrated circuit according to claim 14, wherein the power source voltage generating circuit further comprises: a first P-channel MOS transistor having a source connected to the first voltage terminal, a drain and a gate; a second P-channel MOS transistor having a source connected to the first voltage terminal, a drain connected to the gate of the first P-channel MOS transistor, and a gate; a third P-channel MOS transistor having a source connected to the first voltage level, a gate connected to the gate of the second P-channel MOS transistor and a drain connected to the gate of the third P-channel MOS transistor; a first N-channel MOS transistor having a drain connected to the drain of the first P-channel MOS transistor and the drain of the second P-channel MOS transistor, a gate connected to a reference voltage level input terminal, and a source; a second N-channel MOS transistor having a drain connected to the gate of the second P-channel MOS transistor and the gate and the drain of the third P-channel MOS transistor, a source connected to the source of the first N-channel MOS transistor, and a gate; a third N-channel MOS transistor having a drain connected to the source of the first N-channel MOS transistor and the source of the second N-channel MOS transistor, a gate connected to the gate of the second MOS transistor, and a source connected to the second voltage terminal; a first load element connected between the drain of the first P-channel MOS transistor and the gate of the second N-channel MOS transistor; a second load element connected between the gate of the second N-channel MOS transistor and the second voltage terminal; and a connecting terminal connected between the drain of the first P-channel MOS transistor and the first load element.

Claim 20

A semiconductor integrated circuit according to claim 5, wherein the first load element is a resistor and the second load element is a resistor.

Claim 21

A semiconductor integrated circuit for generating a comparing signal, comprising: a semiconductor substrate; a first voltage terminal connected to a first voltage source; a load element formed in the semiconductor substrate and having two ends, one end of which is connected to the first voltage terminal; a second voltage terminal connected to a second voltage source; an MOS transistor formed in the semiconductor substrate and having a source, a drain, a gate and a channel having no ion-implanted region therein for threshold voltage control; means for connecting the other end of the load element to the source; means for connecting the second voltage terminal to the drain; means for connecting the drain to the gate; an output terminal connected to the other end of the load element and to the source; and a comparing circuit formed in the semiconductor substrate for comparing a value of an external input signal with a value of a reference voltage produced att he output terminal and having at least one MOS transistor which is formed with channel ion-implantation.

Claim 22

A semiconductor integrated circuit for generating a comparing signal, comprising: a semiconductor substrate; a first voltage terminal connected to a first voltage source; a load element formed in the semiconductor substrate and having two ends, one end of which is connected to the first voltage terminal; a second voltage terminal connected to a second voltage source; an MOS transistor formed in the semiconductor substrate and having a source, a drain, a gate and a channel having no ion-implanted region therein for threshold voltage control; means for connecting the other end of the load element to the source; means for connecting the second voltage terminal to the drain; means for connecting the drain to the gate; an output terminal connected to the other end of the load element and to the source; and a comparing circuit formed in the semiconductor substrate for comparing a value of an external input signal with a value of a reference voltage produced att he output terminal and having at least one MOS transistor which is formed with channel ion-implantation.