US5040234A — Apparatus for and method of generating a timing s…

Claim 1

Independent Claim 139 words

An apparatus for generating a timing signal for controlling the operation of an apparatus, comprising: means for generating a clock signal having predetermined cycle; counter means for counting said clock signal to output clock information; rewritable memory means for separately storing a plurality of output data and time data, the stored contents of the memory means being electrically rewritable; rewrite control means responsive to an externally applied rewrite instruction for rewriting the contents of said memory means; and output control means for sequentially reading out at least time information stored in said memory means comparing the read-out time information with the clock information from said counter means to detect an equality therebetween and, the output control means in response to a detected equality, outputting output data stored in memory means corresponding to read-out time information, as the timing signal.

Claim 2

Independent Claim 139 words

An apparatus for generating a timing signal for controlling the operation of an apparatus, comprising: means for generating a clock signal having predetermined cycle; counter means for counting said clock signal to output clock information; rewritable memory means for separately storing a plurality of output data and time data, the stored contents of the memory means being electrically rewritable; rewrite control means responsive to an externally applied rewrite instruction for rewriting the contents of said memory means; and output control means for sequentially reading out at least time information stored in said memory means comparing the read-out time information with the clock information from said counter means to detect an equality therebetween and, the output control means in response to a detected equality, outputting output data stored in memory means corresponding to read-out time information, as the timing signal.

Claim 3

Dependent Claim 40 words

The apparatus according to claim 1, wherein said output control means comprises means for continuously outputting the presently applied output data until another match is detected between the subsequently read-out time information and the clock information from said counter means.

Claim 4

Dependent Claim 30 words

The apparatus according to claim 1, wherein the apparatus is a pulse-driven stepping motor, and said output data comprise data providing a pulse signal waveform which drives said stepping motor.

Claim 5

Dependent Claim 25 words

The apparatus according to claim 3, wherein said stepping motor is a motor for driving a magnetic tape to run in a magnetic recording/reproducing apparatus.

Claim 6

Dependent Claim 13 words

The apparatus of claim 1 wherein said time information is timing signal data.

Claim 7

Independent Claim 229 words

An apparatus for generating a timing signal for controlling the operation of an apparatus: means for generating a clock signal having a predetermined cycle; counter means for counting said clock signal to output clock information; rewritable memory means for separately storing a plurality of output data and time data the stored contents of the memory means being electrically rewritable; rewrite means responsive to an external applied rewrite instruction for rewritting the contents of said memory means; output control means for sequentially reading at least time information in said memory means comparing the read out information with the clock information from said counter means to detect an equality there between and, the output control means in response to a detected equality, outputting output data stored in said memory means corresponding to read out time information, as the timing signal; and first memory means for storing basic output data and basic time data; operation means responsive to said rewrite instruction for reading out basic data in said first memory means to perform a predetermined operation thereon, said rewrite instruction including an instruction for specifying an operation mode for the apparatus, and a predetermined operation of the apparatus being determined according to said operation mode specifying instruction; and means for writing the output data obtained through said operational processing by said operation means and the time information in said rewritable memory means.

Claim 8

Independent Claim 229 words

An apparatus for generating a timing signal for controlling the operation of an apparatus: means for generating a clock signal having a predetermined cycle; counter means for counting said clock signal to output clock information; rewritable memory means for separately storing a plurality of output data and time data the stored contents of the memory means being electrically rewritable; rewrite means responsive to an external applied rewrite instruction for rewritting the contents of said memory means; output control means for sequentially reading at least time information in said memory means comparing the read out information with the clock information from said counter means to detect an equality there between and, the output control means in response to a detected equality, outputting output data stored in said memory means corresponding to read out time information, as the timing signal; and first memory means for storing basic output data and basic time data; operation means responsive to said rewrite instruction for reading out basic data in said first memory means to perform a predetermined operation thereon, said rewrite instruction including an instruction for specifying an operation mode for the apparatus, and a predetermined operation of the apparatus being determined according to said operation mode specifying instruction; and means for writing the output data obtained through said operational processing by said operation means and the time information in said rewritable memory means.

Claim 9

Independent Claim 222 words

An apparatus for generating a timing signal for controlling the operation of an apparatus, comprising: means for generating a clock signal having a predetermined cycle; counter means for counting said clock signal to output clock information; rewritable memory means for separately storing a plurality of output data and time data the stored contents of the memory means being electrically rewritable; rewrite control means responsive to an externally applied rewrite instruction for rewritting the contents of said memory means; output control means for sequentially reading at least time information in said memory means comparing the read out information with the clock information from said counter means to detect an equality there between and, the output control means in response to a detected equality, outputting output data stored in said memory means corresponding to read out time information, as the timing signals; and means for generating a basic clock signal having a predetermined cycle; means for frequency-dividing said basic clock signal, frequency dividing factor of said frequency dividing means being variable; and counter circuit means for counting output of said frequency dividing means to output the count value as clock information which is to be compared with said time information, and wherein said rewrite control means comprises means responsive to said rewrite instruction for setting said frequency dividing factor of said frequency dividing means.

Claim 10

Independent Claim 222 words

An apparatus for generating a timing signal for controlling the operation of an apparatus, comprising: means for generating a clock signal having a predetermined cycle; counter means for counting said clock signal to output clock information; rewritable memory means for separately storing a plurality of output data and time data the stored contents of the memory means being electrically rewritable; rewrite control means responsive to an externally applied rewrite instruction for rewritting the contents of said memory means; output control means for sequentially reading at least time information in said memory means comparing the read out information with the clock information from said counter means to detect an equality there between and, the output control means in response to a detected equality, outputting output data stored in said memory means corresponding to read out time information, as the timing signals; and means for generating a basic clock signal having a predetermined cycle; means for frequency-dividing said basic clock signal, frequency dividing factor of said frequency dividing means being variable; and counter circuit means for counting output of said frequency dividing means to output the count value as clock information which is to be compared with said time information, and wherein said rewrite control means comprises means responsive to said rewrite instruction for setting said frequency dividing factor of said frequency dividing means.

Claim 11

Dependent Claim 52 words

The apparatus according to claim 7, wherein said frequency dividing means comprises: a first counter for counting said basic clock; and means responsive to the frequency dividing factor from said frequency dividing factor setting means for allowing only a selected bit of an output of said first counter output to pass therethrough.

Claim 12

Independent Claim 114 words

A method of generating a timing signal for controlling the operation of an apparatus, comprising the steps of: (a) in response to an externally applied rewrite instruction, separately writing a plurality of output data and time information for storing in a rewritable memory means; (b) counting a clock signal having a predetermined cycle to derive clock information; (c) sequentially reading out at least time information from said rewritable memory means; (d) comparing said read-out time information with the clock information derived in step (b) to detect an equality therebetween; and (e) in response to a detected equality, outputting output data stored in said memory means corresponding to the time information, as the timing signal.

Claim 13

Independent Claim 114 words

A method of generating a timing signal for controlling the operation of an apparatus, comprising the steps of: (a) in response to an externally applied rewrite instruction, separately writing a plurality of output data and time information for storing in a rewritable memory means; (b) counting a clock signal having a predetermined cycle to derive clock information; (c) sequentially reading out at least time information from said rewritable memory means; (d) comparing said read-out time information with the clock information derived in step (b) to detect an equality therebetween; and (e) in response to a detected equality, outputting output data stored in said memory means corresponding to the time information, as the timing signal.

Claim 14

Dependent Claim 37 words

The method according to claim 9, wherein said output step comprises a step of continuously outputting the presently received output data until another match is detected between the subsequently read-out time information and said derived clock information.

Claim 15

Dependent Claim 64 words

The method according to claim 9, wherein said writing step comprises a step of being responsive to said rewrite instruction for performing a predetermined operation on prepared basic output data and basic time information to generate said output data and said time information, said rewrite instruction including an operation mode specifying instruction, and an operation being predetermined according to said operation mode specifying instruction.

Claim 16

Dependent Claim 56 words

The method according to claim 9, wherein said step of deriving the clock information comprises the steps of: frequency-dividing a basic clock signal having a predetermined cycle; and counting said frequency-divided basic clock signal to derive said clock information, the frequency dividing factor of said frequency dividing step being set in response to said rewrite instruction.

Claim 17

Dependent Claim 59 words

The method according to claim 9, wherein said match detecting step comprises a step of allowing count operation for deriving the clock information to overflow and initializing time information reading sequence to read out the time information in a first position for performing match detection, when any read-out time information is smaller than immediately before preceding read-out time information.

Claim 18

Dependent Claim 27 words

The method according to claim 9, wherein the apparatus is a pulse-driven stepping motor, and said timing signal is a pulse-like signal for driving said stepping motor.

Claim 19

Dependent Claim 13 words

The method of claim 9 wherein said time information is timing signal data.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1994-08-12	1995-02-11	1995-08-13	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1998-08-12	1999-02-11	1999-08-13	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2002-08-12	2003-02-11	2003-08-13	$7700.00	Window Closed / Lapsed

Apparatus for and method of generating a timing signal

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