Flip substrate for chip mount

Claim 1

A method for manufacturing an integrated circuit packaging structure comprising the steps of: providing an integrated circuit element including a plurality of internal circuits integrated into a single semi-conductor element, said integrated circuit element having an upper surface and a lower surface, with an array of conductive nodes protruding from said lower surface to provide electrical coupling to said internal circuits; providing a support substrate having an upper surface and a lower surface with a plurality of through vias extending from said upper surface to said lower surface, said through vias being formed in a pattern corresponding to said array of conductive nodes on said lower surface of said integrated circuit element; providing said substrate with conductor means within said through vias extending from said substrate upper surface to said substrate lower surface; providing an electrical interconnect layer with a plurality of electrically conductive interconnect elements distributed within an electrically insulating material, said interconnect layer having an upper surface and a lower surface; further providing said interconnect layer with a plurality of conductive coupling elements extending from, said upper surface to said lower surface of said interconnect layer, said coupling elements being arranged in a pattern corresponding to said array of conductive nodes on said integrated circuit element and being adapted for conductive coupling to said interconnect elements within said interconnect layer and for conductive contact from said lower surface by external sources; and mounting said lower surface of said integrated circuit element adjacent said upper surface of said substrate so as to align said conductive nodes with said through vias and to electrically couple said conductive nodes with said conductor means; mounting said upper surface of said interconnect layer adjacent said lower surface of said substrate so as to align said coupling elements with said through vias and to electrically couple said coupling elements with said conductor means.

Claim 2

A method for manufacturing an integrated circuit packaging structure comprising the steps of: providing an integrated circuit element including a plurality of internal circuits integrated into a single semi-conductor element, said integrated circuit element having an upper surface and a lower surface, with an array of conductive nodes protruding from said lower surface to provide electrical coupling to said internal circuits; providing a support substrate having an upper surface and a lower surface with a plurality of through vias extending from said upper surface to said lower surface, said through vias being formed in a pattern corresponding to said array of conductive nodes on said lower surface of said integrated circuit element; providing said substrate with conductor means within said through vias extending from said substrate upper surface to said substrate lower surface; providing an electrical interconnect layer with a plurality of electrically conductive interconnect elements distributed within an electrically insulating material, said interconnect layer having an upper surface and a lower surface; further providing said interconnect layer with a plurality of conductive coupling elements extending from, said upper surface to said lower surface of said interconnect layer, said coupling elements being arranged in a pattern corresponding to said array of conductive nodes on said integrated circuit element and being adapted for conductive coupling to said interconnect elements within said interconnect layer and for conductive contact from said lower surface by external sources; and mounting said lower surface of said integrated circuit element adjacent said upper surface of said substrate so as to align said conductive nodes with said through vias and to electrically couple said conductive nodes with said conductor means; mounting said upper surface of said interconnect layer adjacent said lower surface of said substrate so as to align said coupling elements with said through vias and to electrically couple said coupling elements with said conductor means.

Claim 14

A method of manufacturing an integrated circuit packaging structure comprising the steps of: providing an integrated circuit element with a plurality of internal circuits integrated into a single semi-conductor element, said integrated circuit element having an upper surface, a lower surface and a peripheral edge; further providing said integrated circuit element with a plurality of conductive leads extending from said peripheral edge to provide electrical coupling to said internal circuits; providing a support substrate having an upper surface and a lower surface with a plurality of through vias extending from said upper surface to said lower surface, said through vias being formed in a pattern corresponding to the arrangement of said conductive leads of said integrated circuit element; providing said substrate with conductor means within said through vias and extending from said substrate upper surface to said substrate lower surface; providing an electrical interconnect layer comprising a plurality of electrically conductive interconnect elements distributed within an electrically insulating material, said interconnect layer having an upper surface and a lower surface; further providing said interconnect layer with a plurality of conductive coupling elements extending from said upper surface to said lower surface of said interconnect layer, said coupling elements being arranged in a pattern corresponding to the arrangement of said conductive leads of said integrated circuit element and being adapted for conductive coupling to said interconnect elements within said interconnect layer and for conductive contact from said lower surface by external sources; and mounting said lower surface of said integrated circuit element adjacent said upper surface of said substrate so as to align said conductive leads with said through vias and to electrically couple said conductive leads with said conductor means; mounting said upper surface of said interconnect layer adjacent said lower surface of said substrate so as to align said coupling elements with said through vias and to electrically couple said coupling elements with said conductor means.

Claim 15

A method of manufacturing an integrated circuit packaging structure comprising the steps of: providing an integrated circuit element with a plurality of internal circuits integrated into a single semi-conductor element, said integrated circuit element having an upper surface, a lower surface and a peripheral edge; further providing said integrated circuit element with a plurality of conductive leads extending from said peripheral edge to provide electrical coupling to said internal circuits; providing a support substrate having an upper surface and a lower surface with a plurality of through vias extending from said upper surface to said lower surface, said through vias being formed in a pattern corresponding to the arrangement of said conductive leads of said integrated circuit element; providing said substrate with conductor means within said through vias and extending from said substrate upper surface to said substrate lower surface; providing an electrical interconnect layer comprising a plurality of electrically conductive interconnect elements distributed within an electrically insulating material, said interconnect layer having an upper surface and a lower surface; further providing said interconnect layer with a plurality of conductive coupling elements extending from said upper surface to said lower surface of said interconnect layer, said coupling elements being arranged in a pattern corresponding to the arrangement of said conductive leads of said integrated circuit element and being adapted for conductive coupling to said interconnect elements within said interconnect layer and for conductive contact from said lower surface by external sources; and mounting said lower surface of said integrated circuit element adjacent said upper surface of said substrate so as to align said conductive leads with said through vias and to electrically couple said conductive leads with said conductor means; mounting said upper surface of said interconnect layer adjacent said lower surface of said substrate so as to align said coupling elements with said through vias and to electrically couple said coupling elements with said conductor means.

Claim 19

A method of manufacturing an integrated circuit packaging structure of the type adapted to receive an integrated circuit element including a plurality of internal circuits integrated into a single semi-conductor element, the single semi-conductor element being of the type having an upper surface and a lower surface and being formed having an array of conductive nodes protruding from the lower surface to provide electrical coupling to the internal circuits, said packaging structure method comprising the steps of: providing a support substrate having an upper surface and a lower surface; forming a plurality of through vias in said substrate extending from said upper surface to said lower surface in a pattern corresponding to the array of conductive nodes of the lower surface of the integrated circuit element; providing conductor means within said through vias extending from said substrate upper surface to said substrate lower surface; providing an electrical interconnect layer having a plurality of electrically conductive interconnect elements distributed within an electrically insulating material, and having an upper surface and a lower surface with a plurality of conductive coupling elements extending from said upper surface to said lower surface of said interconnect layer; and wherein said coupling elements are arranged in a pattern corresponding to the array of conductive nodes on the integrated circuit element and adapted for conductive coupling to said interconnect elements within said interconnect layer and for conductive contact from said lower surface by external sources; and mounting the lower surface of the integrated circuit element adjacent the upper surface of the substrate so as to align the conductive nodes with said through vias and to electrically couple the conductive nodes with said conductor means; mounting said upper surface of said interconnect layer adjacent said lower surface of said substrate so as to align said coupling elements with said through vias and to electrically couple said coupling elements with said conductor means.

Claim 20

A method of manufacturing an integrated circuit packaging structure of the type adapted to receive an integrated circuit element including a plurality of internal circuits integrated into a single semi-conductor element, the single semi-conductor element being of the type having an upper surface and a lower surface and being formed having an array of conductive nodes protruding from the lower surface to provide electrical coupling to the internal circuits, said packaging structure method comprising the steps of: providing a support substrate having an upper surface and a lower surface; forming a plurality of through vias in said substrate extending from said upper surface to said lower surface in a pattern corresponding to the array of conductive nodes of the lower surface of the integrated circuit element; providing conductor means within said through vias extending from said substrate upper surface to said substrate lower surface; providing an electrical interconnect layer having a plurality of electrically conductive interconnect elements distributed within an electrically insulating material, and having an upper surface and a lower surface with a plurality of conductive coupling elements extending from said upper surface to said lower surface of said interconnect layer; and wherein said coupling elements are arranged in a pattern corresponding to the array of conductive nodes on the integrated circuit element and adapted for conductive coupling to said interconnect elements within said interconnect layer and for conductive contact from said lower surface by external sources; and mounting the lower surface of the integrated circuit element adjacent the upper surface of the substrate so as to align the conductive nodes with said through vias and to electrically couple the conductive nodes with said conductor means; mounting said upper surface of said interconnect layer adjacent said lower surface of said substrate so as to align said coupling elements with said through vias and to electrically couple said coupling elements with said conductor means.

Claim 21

A method of manufacturing an integrated circuit packaging structure of the type adapted to receive an integrated circuit element including a plurality of internal circuits integrated into a single semi-conductor element, the semi-conductor element being formed having an upper surface a lower surface, and a peripheral edge and having a plurality of conductive leads extending from the peripheral edge to provide electrical coupling to the internal circuits, said method comprising the steps of: providing a support substrate having an upper surface and a lower surface with a plurality of through vias formed therein extending from said upper surface to said lower surface, said through vias being formed in a pattern corresponding to the arrangement of the conductive leads of the integrated circuit element; further providing said substrate with conductor means within said through vias extending from said substrate upper surface to said substrate lower surface; providing an electrical interconnect layer comprising a plurality of electrically conductive interconnect elements distributed within an electrically insulating material, said interconnect layer having an upper surface and a lower surface; providing said interconnect layer with a plurality of conductive coupling elements extending from said upper surface to said lower surface of said interconnect layer, said coupling elements being arranged in a pattern corresponding to the arrangement of the conductive leads of the integrated circuit element and being adapted for conductive coupling to said interconnect elements within said interconnect layer and for conductive contact from said lower surface by external sources; and mounting the lower surface of said integrated circuit element adjacent said upper surface of said substrate so as to align said conductive leads with said through vias and to electrically couple said conductive leads with said conductor means; mounting said upper surface of said interconnect layer adjacent said lower surface of said substrate so as to align said coupling elements with said through vias and to electrically couple said coupling elements with said conductor means.

Claim 22

A method of manufacturing an integrated circuit packaging structure of the type adapted to receive an integrated circuit element including a plurality of internal circuits integrated into a single semi-conductor element, the semi-conductor element being formed having an upper surface a lower surface, and a peripheral edge and having a plurality of conductive leads extending from the peripheral edge to provide electrical coupling to the internal circuits, said method comprising the steps of: providing a support substrate having an upper surface and a lower surface with a plurality of through vias formed therein extending from said upper surface to said lower surface, said through vias being formed in a pattern corresponding to the arrangement of the conductive leads of the integrated circuit element; further providing said substrate with conductor means within said through vias extending from said substrate upper surface to said substrate lower surface; providing an electrical interconnect layer comprising a plurality of electrically conductive interconnect elements distributed within an electrically insulating material, said interconnect layer having an upper surface and a lower surface; providing said interconnect layer with a plurality of conductive coupling elements extending from said upper surface to said lower surface of said interconnect layer, said coupling elements being arranged in a pattern corresponding to the arrangement of the conductive leads of the integrated circuit element and being adapted for conductive coupling to said interconnect elements within said interconnect layer and for conductive contact from said lower surface by external sources; and mounting the lower surface of said integrated circuit element adjacent said upper surface of said substrate so as to align said conductive leads with said through vias and to electrically couple said conductive leads with said conductor means; mounting said upper surface of said interconnect layer adjacent said lower surface of said substrate so as to align said coupling elements with said through vias and to electrically couple said coupling elements with said conductor means.