Apparatus and method for executing a conditional branch instruction

Claim 1

Apparatus for executing a conditional branch instruction for use in a computer system of the type that includes memory means for storing data, including instructions, the memory means further including means for providing the stored data in response to a memory address, the conditional branch instruction defining a branch condition and a branch address of a target instruction, the apparatus for executing a conditional branch instruction comprising: instruction queue means coupled to the memory means for receiving an instruction stream therefrom and including means for storing portions of the instructions prior to execution of the instructions, wherein a beginning portion of an instruction includes a part or all of a next instruction to be executed, the beginning portion being stored, during a first cycle which is a last cycle of execution of a preceding instruction, at a head of the instruction queue means, the instruction queue means further including means, responsive to an occurrence of a dispatch operation during the first cycle, for outputting the beginning portion and for advancing a following portion contained in the instruction queue means to the head of the instruction queue means, the instruction queue means further including means, responsive to an occurrence of a conditional fetch operation, for loading a target instruction of the conditional fetch operation into the head of the instruction queue means unless completion of the conditional fetch operation is inhibited; first address computation means, coupled to the head of the instruction queue means and also to the memory means, for responding to the dispatch operation, the first address computation means including means for computing an address defined in the beginning portion and also including means for retaining the computed address, the first address computation means, when the beginning portion is associated with a conditional branch instruction, to compute a branch address; and instruction interpretation means, coupled to the head of the instruction queue means and to the first address computation means, for causing performance of the dispatch operation, the instruction interpretation means including means for receiving the beginning portion in the first cycle and, responsive to the receipt of the beginning portion within the first cycle, for initiating an interpretation of the beginning portion in a second cycle immediately following the first cycle, the instruction interpretation means further including means, responsive during the second cycle when the beginning portion is interpreted to be a conditional branch instruction, for performing a conditional fetch operation using the retained computed address and for determining whether a branch condition indicates that the conditional branch is to be taken, wherein if the conditional branch is determined not to be taken, the instruction interpretation means includes means for inhibiting, during the second cycle, a completion of the conditional fetch operation and for causing instead the dispatch operation to be performed, or if the conditional branch is determined to be taken, the instruction interpretation means includes means for permitting, during the second cycle, a completion of the conditional fetch operation and for causing the dispatch operation to be performed during a third cycle that immediately follows the second cycle.