Self-mounted chip carrier

Claim 2

A self-mounted chip carrier, comprising: a surface containing the integrated circuit and having a contact pad metallized area; a registration means for securing said carrier to a mating substrate and for aligning a mating pad on the chip carrier with a mating pad on the substrate, said registration means located away from the contact pad metallized area; a compliant connector between the carrier and the substrate, said connector made from an elastomeric material; and a lid serving as a deflection stop.

Claim 3

The self-mounted chip carrier of claim 1, wherein said positioning means comprises bolt members.

Claim 4

The self-mounted chip carrier of claim 2, wherein said bolt members are shouldered.

Claim 5

The self-mounted chip carrier of claim 3, wherein said bolt members are located in diametrically opposed corners of said surface.

Claim 6

The self-mounted chip carrier of claim 4, wherein said means for securing is a shouldered screw.

Claim 7

The self-mounted chip carrier of claim 5, wherein said elastomeric connector comprises a plurality of linear strips.

Claim 8

The self-mounted chip carrier of claim 5, wherein said elastomeric connector is a metal-on-elastomer ring.

Claim 9

The self-mounted chip carrier of claim 7, wherein said metal-on-elastomer ring is configured in a matrix formation.

Claim 10

The self-mounted chip carrier of claim 5, wherein said elastomeric connector is metallic.

Claim 11

The self-mounted chip carrier of claim 9, wherein said elastomeric connector is adapted to fit into spaces in a molded ring.

Claim 12

A self-mounted chip carrier, comprising a contact pad metallized substrate containing an integrated circuit; registration holes on diametrically opposed ends of the substrate; shouldered bolt members, adapted to fit into said holes, for aligning and securing the carrier to an electronic substrate; a compliant elastomeric metal-on-elastomer ring configured in a matrix formation, wherein said ring contacts said contact pad; and a lid to retain said chip in position and to decrease deflection of said metal-on-elastomer ring.

Claim 13

A self-mounted chip carrier, comprising a contact pad metallized substrate containing an integrated circuit; registration holes on diametrically opposed ends of the substrate; shouldered bolt members, adapted to fit into said holes, for aligning and securing the carrier to an electronic substrate; a compliant elastomeric metal-on-elastomer ring configured in a matrix formation, wherein said ring contacts said contact pad; and a lid to retain said chip in position and to decrease deflection of said metal-on-elastomer ring.

Claim 14

An electronics assembly comprising: a chip carrier having a first set of contacts and a first set of alignment holes and including an integrated circuit positioned in the surface on which said first set of contacts is positioned; an electronic substrate having a second set of contacts and a second set of alignment holes; compliant connecting means positioned between said chip carrier and said electronic substrate for connecting selected contacts of said first set of contacts to selected contacts of said second set of contacts, said compliant connecting means including a ring of elastomeric elements; a lid positioned to protect said integrated circuit and fitted within said ring of elastomeric elements to restrict inward deflection of said ring of elastomeric elements; and a plurality of screws each extending through an alignment hole in said chip carrier and an alignment hole in said electronic substrate for aligning said first set and said second set of contacts and assembling said chip carrier and said electronic substrate with said selected contacts connected by said compliant connecting means.

Claim 15

An electronics assembly comprising: a chip carrier having a first set of contacts and a first set of alignment holes and including an integrated circuit positioned in the surface on which said first set of contacts is positioned; an electronic substrate having a second set of contacts and a second set of alignment holes; compliant connecting means positioned between said chip carrier and said electronic substrate for connecting selected contacts of said first set of contacts to selected contacts of said second set of contacts, said compliant connecting means including a ring of elastomeric elements; a lid positioned to protect said integrated circuit and fitted within said ring of elastomeric elements to restrict inward deflection of said ring of elastomeric elements; and a plurality of screws each extending through an alignment hole in said chip carrier and an alignment hole in said electronic substrate for aligning said first set and said second set of contacts and assembling said chip carrier and said electronic substrate with said selected contacts connected by said compliant connecting means.