US5033066A
Expired / Lapsed
US
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Event tagging time delay
Assignee: Raytheon Co
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Filing: 1990-02-16
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Granted: 1991-07-16
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Expires: 2010-02-16
Abstract
Abstract A time delay circuit for providing a delayed replica of a digital input signal including first and second counters for providing first and second count outputs offset relative to each other by a predetermined value indicative of a predetermined delay, and further including a first-in first-out (FIFO) memory for controllably storing selected values of the digital input signal together with corresponding first count output values. First comparison circuitry compares each digital input with the immediately prior digital input, and controls the FIFO memory to store (a) each digital input which is different from the immediately prior digital input, and (b) the first counter output value associated therewith. The FIFO memory circuit provides an output comprising (1) a digital output that corresponds to the earliest changed digital output which has not yet been utilized in the delayed replica of the digital input signal, and (2) a FIFO count output that corresponds to the first counter output value associated with such digital output. Second comparison circuitry responsive to the second counter output and the FIFO count output controls the FIFO memory circuit to change its output when the second counter output and the FIFO count output are equal.
Inventors
- 👤 Doug DeVore
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:32
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/131; H03K5/135; H03K2005/00013; H03K2005/00019; H03K2005/00058; H03K2005/0015; H03K2005/00234; H03K2005/00247; H03K2005/0026; H03K2005/00273
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
227 words
A time delay circuit for providing a delayed replica of a digital input signal, comprising: a first counter responsive to a reference clock signal for providing a first counter output; a second counter responsive to said reference clock signal and synchronized to said first counter for providing a second counter output, said second counter output being offset relative to said first counter output by a predetermined value which corresponds to a predetermined delay; data storage means for storing selected values of said digital input signal together with corresponding first counter output values, and for controllably outputting the stored values in the same sequence they were stored; first comparison means responsive to the digital input signal for comparing each digital input with the immediately preceding digital input, and for controlling said storage means to store (a) each digital input which is different from the immediately preceding digital input, and (b) the first counter output value associated therewith, whereby the output of said storage means comprises (1) a digital output and (2) a storage means count output that corresponds to the first counter output value associated with such digital output; and second comparison means responsive to said second counter output and said storage means count output for controlling said storage means circuit to change its output when said second counter output and said storage means count output are equal.
Claim 2
Dependent Claim
227 words
A time delay circuit for providing a delayed replica of a digital input signal, comprising: a first counter responsive to a reference clock signal for providing a first counter output; a second counter responsive to said reference clock signal and synchronized to said first counter for providing a second counter output, said second counter output being offset relative to said first counter output by a predetermined value which corresponds to a predetermined delay; data storage means for storing selected values of said digital input signal together with corresponding first counter output values, and for controllably outputting the stored values in the same sequence they were stored; first comparison means responsive to the digital input signal for comparing each digital input with the immediately preceding digital input, and for controlling said storage means to store (a) each digital input which is different from the immediately preceding digital input, and (b) the first counter output value associated therewith, whereby the output of said storage means comprises (1) a digital output and (2) a storage means count output that corresponds to the first counter output value associated with such digital output; and second comparison means responsive to said second counter output and said storage means count output for controlling said storage means circuit to change its output when said second counter output and said storage means count output are equal.
Claim 3
Dependent Claim
16 words
The time delay circuit of claim 1 wherein said storage means comprises a first-in first-out memory.
Claim 4
Dependent Claim
64 words
The time delay circuit of claim 1 wherein said first comparison means comprises: a register for controllably storing selected values of the digital input signal; and a comparator circuit for comparing the contents of said register with the present value of the digital input signal, said register being loaded with the present value of the the digital input signal when the comparison indicates inequality.
Claim 5
Dependent Claim
29 words
The time delay circuit of claim 3 wherein said comparator controls said storage means to load the present value of the digital input signal when the comparison indicates inequality.
Claim 6
Dependent Claim
47 words
The time delay circuit of claim 1 wherein said second comparison means comprises: a comparator circuit for comparing said second counter output and said storage means count output; and gating means responsive to said comparator circuit for providing a gating signal when said comparator circuit indicates equality.
Claim 7
Dependent Claim
29 words
The time delay circuit of claim 5 wherein said gating signal is coupled to said storage means and causes said storage means to provide the output next in sequence.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-15 | 1995-01-14 | 1995-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-15 | 1999-01-14 | 1999-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-15 | 2003-01-14 | 2003-07-16 | $7700.00 | Window Closed / Lapsed |